QL5064 QuickPCI Data Sheet
Expanded PCI Functionality
• Support for Configuration Space from 0x40 to 0x3FF
• PCI expanded capabilities support
• Expansion ROM supported with back-end memory
• Power management support
• Compact PCI hot-swap/hot-plug compliant
• Messaged Interrupts
• Configuration specified with anti-fuses on board, external EEPROM not needed
Programmable Logic
• 192 Programmable I/O pins in a 456 pin or 484 pin PBGA package
• 74K gates with 11 blocks (total of 12,672 bits) of dual-port RAM
• 250 MHz 16-bit counters, 275 MHz Datapaths, 160 MHz FIFOS
• All back-end interface and glue-logic can be implemented
on chip
PCI Bus - 33/66/75 MHz 32/64 Bits (Data and Address)
3 RECV
FIFOs
64 deep
4 Channel
DMA Ctrl
3 XMIT
FIFOs
64 deep
PCI CONTROLLER
Interrupts
Messaging
Config.
64
64
64
100 MHz INTERFACE
192 User I/O
High Speed Logic Cells
74K Gates
12k bits
Dual Port RAM
PROGRAMMABLE LOGIC
Figure 1: QL5064 Block Diagram
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© 2002 QuickLogic Corporation