QL5064-66BPB456I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5064-66BPB456I
QuickLogic Corporation
'QL5064-66BPB456I' PDF : 37 Pages View PDF
QL5064 QuickPCI Data Sheet
9.0 DataIN Bus Description
The DataIN bus is used to transfer data from the PCI bus to the back-end interface. This data can come
from three different data paths: one of the two DMA receive FIFOs, or the Target Write/Post FIFO. For
proper data management, empty and almost empty flags from the two DMA receive FIFOs are available
to the back-end design. The almost empty flags are fully configurable via the Control_DATA bus
interface or the PCI bus. Interface to the Target Write/Post FIFO is accomplished through the Target
interface signals. A block diagram of the DataIN and Target control connections is seen in Figure 6.
Data is transferred to the DataIN bus in the same byte lane in which is was transferred over the PCI bus.
To assist with re-aligning or compacting data in the back-end interface, a byte-lane barrel shifter provides
the means to manipulate byte lane positioning. This is accomplished with the byte_select[2:0] input.
See the DataIN Bus section of the internal signal descriptions for more information.
pci data
64
pci cbe [7:0]
8
Target/
Write
Post FIFO
(32 Deep)
Byte lane [7:0]
0
Lane
1
64 Barrel
2
3
Shifter
FPGA
DQ
64
dataIN [63:0]
64
DMA Rcv 0
FIFO
(64 deep)
8
Byte lane [7:0]
Chain Descriptor Tags
64
DMA Rcv 1
or Target Write
Post FIFO
(64 Deep)
8
Byte lane [7:0]
2
0
1
8
2
Shifter
3
2
DQ
DQ
rcv0_fifo_program_empty_flag
rcv0_fifo_ef
3
dataIN_bytesel [2:0]
dataIN_BE[7:0]
dataIN_byteID [1:0]
rcv1_fifo_program_empty_flag
rcv1_fifo_ef
2
0
1
2
dataIN_src_sel[1:0]
dataIN_cs
user_clk
Figure 6: DataIN Bus Description
QL5064 QuickPCI Data Sheet Rev D
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