QL5332-33APQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5332-33APQ208C
QuickLogic Corporation
'QL5332-33APQ208C' PDF : 25 Pages View PDF
QL5332 QuickPCI Data Sheet
• • • • • • 33 MHz/32-Bit PCI Master/Target with Embedded
Programmable Logic and Dual Port SRAM
Device Highlights
High Performance PCI Controller
QL5332 supports new enhanced features added to
QL5032:
• All PCI commands (including configuration and
MWI)
• Fully-customizable byte enables as a master
• Zero-wait-state write and one-wait-state read
Target interface
• Target interface supports retry, disconnect
with/without data transfer, and target abort
• Target aborts
• Has 125 more logic cells in FPGA section, but
2 less RAM blocks
• Pin compatible with QL5032
QL5332 also supports the original features of
QL5032:
• 32-bit/33 MHz PCI Master/Target
• Zero-wait state PCI Master provides 132 MBps
transfer rates
• Programmable back-end interface to optional
local processor
• Independent PCI bus (33 MHz) and local bus
(up to 160 MHz) clocks
• Fully customizable PCI configuration space
• Configurable FIFOs with depths up to 256
• Reference design with driver code
(Win 95/98/2000/NT4.0) available
• PCI v2.2 compliant
• Supports Type 0 configuration cycles in Target
mode
• 3.3 V, 5 V tolerant PCI signaling supports
universal PCI adapter designs
• 3.3 V CMOS in 208-pin PQFP and 256-pin
PBGA
• Supports endian conversions
• Unlimited/continuous burst transfers supported
Extendable PCI Functionality
• Support for configuration space from 0x40 to
0x3FF
• Multi-function, expanded capabilities, and
expansion ROM capable
• Power management, compact PCI, hot-
swap/hot-plug compatible
• PCI v2.2 Power Management Spec compatible
• PCI v2.2 Vital Product Data (VPD) configuration
support
Programmable logic
• 515 logic cells
• 13,824 RAM bits, up to 154 I/O pins
• 250 MHz 16-bit counters, 275 MHz Datapaths,
160 MHz FIFOs
• All back-end interface and glue-logic can be
implemented on chip
• Any combination of FIFOs that require 12 or less
QuickLogic RAM modules
• Six 32-bit busses interface between the PCI
Controller and the Programmable Logic
Figure 1: QL5332 Block Diagram
PCI Bus 33 MHz/32 bits (data and address)
PCI Controller
Master
Controller
High
Speed
Data
Path
Target
Controller
32 bit Interface
Programmable
Logic
160 MHz
154 User I/O
FIFOs
High Speed
Logic Cells
PCI Bus
Config.
Space
DMA
Controller
© 2004 QuickLogic Corporation
www.quicklogic.com
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