QL5332-33APQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5332-33APQ208C
QuickLogic Corporation
'QL5332-33APQ208C' PDF : 25 Pages View PDF
QL5332 QuickPCI Data Sheet Rev. C
JTAG Support
JTAG pins support IEEE standard 1149.1a to provide boundary scan capability for the QL5332 device. Six
pins are dedicated to JTAG and programming functions on each QL5332 device, and are unavailable for
general design input and output signals. TDI, TDO, TCK, TMS, and TRSTB are JTAG pins. A sixth pin, STM,
is used only for programming.
Development Tools
Software support for the QL5332 device is available through the QuickWorks development package.
QuickWorks is fully integrated into the Windows 98, 2000, NT, ME and XP operating systems. It provides
design, layout, pre- and post-layout simulation and external stimulus design tools as shown in Figure 4. The
program that links all these applications together and acts as the design flow manager is called Seamless pASIC
Design Environment (SpDE). The term “pASIC” is a registered trademark of QuickLogic Corporation and
refers to a QuickLogic FPGA, or “programmable ASIC.”
QuickWorks can be used to perform the following functions in the design process:
• Design
• Pre-layout Simulation
• Synthesis
• Placement and Optimization
• Post-layout Simulation
The UNIX-based QuickTools package is a subset of QuickWorks and provides a solution for designers who
use schematic-only design flow third-party tools for design entry, synthesis, or simulation. QuickTools reads
EDIF netlists and provides support for all QuickLogic devices. QuickTools also supports a wide range of third-
party modeling and simulation tools.
© 2004 QuickLogic Corporation
www.quicklogic.com
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