QL5332-33APQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5332-33APQ208C
QuickLogic Corporation
'QL5332-33APQ208C' PDF : 25 Pages View PDF
QL5332 QuickPCI Data Sheet Rev. C
AC Characteristics
The AC Specifications (at VCC = 3.3 V, TA = 25° C (K = 1.00)) are provided in Table 10 through
Table 17.
(To calculate delays, multiply the appropriate K factor in Table 8 operating ranges by the following numbers.)
Table 10: Logic Cells
Symbol
Parameter
Propagation Delays (ns)
Fanouta
1
2
3
4
8
tPD
Combinatorial Delay of the longest path: time taken by
the combinatorial circuit to outputb
1.4
1.7
2.0
2.3
3.5
tSU
Setup time: time the synchronous input of the flip-flop
must be stable before the active clock edgeb
1.8
1.8
1.8
1.8
1.8
tH
Hold time: time the synchronous input of the flip-flop
must be stable after the active clock edge
0.0
0.0
0.0
0.0
0.0
tCLK
Clock-to-Q delay: the amount of time taken by the flip-
flop to output after the active clock edge.
0.8
1.1
1.4
1.7
2.9
tCWHI
Clock High Time: required minimum time the clock stays
high
1.6
1.6
1.6
1.6
1.6
tCWLO
Clock Low Time: required minimum time that the clock
stays low
1.6
1.6
1.6
1.6
1.6
tSET
Set Delay: time between when the flip-flop is ”set” (high)
and when the output is consequently “set” (high)
1.4
1.7
2.0
2.3
3.5
tRESET
Reset Delay: time between when the flip-flop is ”reset”
(low) and when the output is consequently “reset” (low)
1.2
1.5
1.8
2.1
3.3
tSW
Set Width: time that the SET signal must remain
high/low
1.9
1.9
1.9
1.9
1.9
tRW
Reset Width: time that the RESET signal must remain
high/low
1.8
1.8
1.8
1.8
1.8
a. Stated timing for worst case Propagation Delay over process variation at VCC=3.3 V and TA=25×C. Multiply by the
appropriate Delay Factor, K, for speed grade, voltage and temperature settings as specified in the Operating Range.
b. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell
including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of
your particular design.
16
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