QL5332-33APQ208C View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5332-33APQ208C

33 MHz/32-Bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

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QL5332 QuickPCI Data Sheet Rev. C

Table 6: QL5332 External Device Pins (Continued)

REQN

GNTN

PERRN

SERRN

IDSEL

IRDYN

TRDYN

STOPN

INTAN

T/S

IN

S/T/S

O/D

IN

S/T/S

S/T/S

S/T/S

O/D

PCI Request. Indicates to the Arbiter that this PCI Agent (Initiator) needs to use the bus. A

point-to-point signal between the PCI device and the System Arbiter.

PCI Grant. Indicates to a PCI Agent (Initiator) that it has been granted access to the PCI bus

by the Arbiter. A point-to-point signal between the PCI device and the System Arbiter.

PCI Data Parity Error. Driven active by the initiator or target two clock cycles after a data parity

error is detected on the AD and C/BEN busses.

PCI System Error. Driven active when an address cycle parity error, data parity error during a

special cycle, or other catastrophic error is detected.

PCI Initialization Device Select. Use to select a specific PCI Agent during System Initialization.

PCI Initiator Ready. Indicates the Initiator’s ability to complete a read or write transaction. Data

transfer occurs only on clock cycles where both IRDYN and TRDYN are active.

PCI Target Ready. Indicates the Target’s ability to complete a read or write transaction. Data

transfer occurs only on clock cycles where both IRDYN and TRDYN are active.

PCI Stop. Used by a PCI Target to end a burst transaction.

Interrupt A. Asynchronous Active-Low Interrupt Request.

a. See Quick Note 65 at http://quicklogic.com/images/quicknote65.pdf for information on RAM initialization.

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