QL5332-33APQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5332-33APQ208C
QuickLogic Corporation
'QL5332-33APQ208C' PDF : 25 Pages View PDF
QL5332 QuickPCI Data Sheet Rev. C
QL5332 External Device Pins
Table 5 describes the different types of devices pins. Table 6 describes the external pins on the QL5332
device, some of which connect to the PCI bus, and others that are programmable as user IO.
Type
IN
OUT
T/S
S/T/S
O/D
Table 5: Pin Types
Description
Input. A standard input-only signal
Totem pole output. A standard active output driver
Tri-state. A bi-directional, tri-state input/output pin
Sustained Tri-state. An active low tri-state signal driven by one PCI agent at a time. It must be driven
high for at least one clock before being disabled (set to Hi-Z). A pull-up needs to be provided by the PCI
system central resource to sustain the inactive state once the active driver has released the signal.
Open Drain. Allows multiple devices to share this pin as a wired-or.
Table 6: QL5332 External Device Pins
Pin/Bus
Name
VCC
VCCIO
GND
I/O
GLCK/I
ACLK/I
TDI/RSIa
TDO/RCOa
TCK
TMS
TRSTB/RROa
STM
AD[31:0]
CBEN[3:0]
PAR
FRAMEN
DEVSELN
CLK
RSTN
Type
IN
IN
IN
T/S
IN
IN
IN
OUT
IN
IN
IN
IN
T/S
T/S
T/S
S/T/S
S/T/S
IN
IN
Function
Supply Pin. Tie to 3.3V supply.
Supply Pin for I/O. Set to 3.3V for 3.3V I/O, 5V for 5.0V compliant I/O.
Ground Pin. Tie to GND on the PCB.
Programmable Input/Output/Tri-State/Bi-directional Pin.
Programmable Global Network or Input-Only Pin. Tie to VCC or GND if unused.
Programmable Array Network or Input-Only Pin. Tie to VCC or GND if unused.
JTAG Data In/RAM Init. Serial Data In. Tie to VCC if unused. Connect to Serial EPROM data
for RAM init.
JTAG Data Out/RAM Init. Clock. Leave unconnected if unused. Connect to Serial EPROM
clock for RAM init.
JTAG Clock. Tie to GND if unused.
JTAG Test Mode Select. Tie to VCC if unused.
JTAG Reset/RAM Init. Reset Out. Tie to GND if unused. Connect to Serial EPROM reset for
RAM init.
QuickLogic Reserved Pin. Tie to GND on the PCB.
PCI Address and Data. 32 bit multiplexed address/data bus.
PCI Bus Command and Byte Enables. Multiplexed bus which contains byte enables for
AD[31:0] or the Bus Command during the address phase of a PCI transaction.
PCI Parity. Even Parity across AD[31:0] and C/BEN[3:0] busses. Driven one clock after
address or data phases. Master drives PAR on address cycles and PCI writes. The Target
drives PAR on PCI reads.
PCI Cycle Frame. Driven active by current PCI Master during a PCI transaction. Driven low to
indicate the address cycle, driven high at the end of the transaction.
PCI Device Select. Driven by a Target that has decoded a valid base address.
PCI System Clock Input.
PCI System Reset Input.
© 2004 QuickLogic Corporation
www.quicklogic.com
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