QL5332-33APQ208C View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5332-33APQ208C

33 MHz/32-Bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

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QL5332 QuickPCI Data Sheet Rev. C

Table 15: Clock Cells

Symbol

Parameter

tACK

tGCKP

tGCKB

Array clock delay

Global clock pin delay

Global clock buffer delay

Propagation Delays (ns)

Fanouta

1

2

3

4

8

10 12 15

1.2 1.2 1.3 1.3 1.5 1.6 1.7 1.8

0.7 0.7 0.7 0.7 0.7 0.7 0.7 0.7

0.8 0.8 0.9 0.9 1.1 1.2 1.3 1.4

a. The array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half

columns, each driven by an independent buffer. The number of half columns used does not affect clock buffer delay.

The array clock has up to 8 loads per half column. The global clock has up to 11 loads per half column.

Table 16: I/O Cell Input Delays

Symbol

Parameter

Propagation Delays (ns)

Fanouta

1

2

3

4

8

10

tI/O Input delay (bidirectional pad)

1.3 1.6 1.8 2.1 3.1 3.6

tISU

Input register setup time: time the synchronous input of the

flip-flop must be stable before the active clock edge

3.1

3.1

3.1

3.1

3.1

3.1

tIH

Input register hold time: time the synchronous input of the

flip-flop must be stable after the active clock edge

0.0

0.0

0.0

0.0

0.0

0.0

tIOCLK Input register clock-to-Q

0.7 1.0 1.2 1.5 2.5 3.0

Input register reset delay: time between when the flip-flop is

tIORST “reset”(low) and when the output is consequently “reset”

(low)

0.6 0.9 1.1 1.4 2.4 2.9

tIESU

Input register clock enable setup time: time “enable” must be

stable before the active clock edge

2.3

2.3

2.3

2.3

2.3

2.3

tIEH

Input register clock enable hold time: time “enable” must be

stable after the active clock edge

0.0

0.0

0.0

0.0

0.0

0.0

a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell

including typical net delays. Worst case delay values for specific paths should be determined from timing analysis of

a particular design.

Table 17: I/O Cell Output Delays

Symbol

Parameter

tOUTLH

tOUTHL

tPZH

Output Delay low to high (90% of H)

Output Delay high to low (10% of L)

Output Delay tri-state to high (90% of H)

Propagation Delays (ns)

Output Load Capacitance (pF)

30 50 75 100 150

2.1 2.5 3.1 3.6 4.7

2.2 2.6 3.2 3.7 4.8

1.2 1.7 2.2 2.8 3.9

© 2004 QuickLogic Corporation

www.quicklogic.com

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