QL5332-33APQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5332-33APQ208C
QuickLogic Corporation
'QL5332-33APQ208C' PDF : 25 Pages View PDF
QL5332 QuickPCI Data Sheet Rev. C
Table 13: RAM Cell Synchronous Read Timing
Symbol
Parameter
Propagation Delays (ns)
Fanout
1
2
3
4
8
rPDRD
RA to RD: time between when the READ ADDRESS is
input and when the DATA is outputa
3.0
3.3
3.6
3.9
5.1
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including
typical net delays. Worst case delay values for specific paths should be determined from timing analysis of a particular
design.
Table 14: Input-Only Cells
Symbol
Parameter
Propagation Delays (ns)
Fanouta
1
2
3
4
8
12 24
tIN High drive input delay
1.5 1.6 1.8 1.9 2.4 2.9 4.4
tINI High drive input, inverting delay
1.6 1.7 1.9 2.0 2.5 3.0 4.5
Input register setup time: time the synchronous input
tISU of the flip-flop must be stable before the active clock 3.1 3.1 3.1 3.1 3.1 3.1 3.1
edge
Input register hold time: time the synchronous input
tIH of the flip-flop must be stable after the active clock 0.0 0.0 0.0 0.0 0.0 0.0 0.0
edge
tICLK Input register clock-to-Q
0.7 0.8 1.0 1.1 1.6 2.1 3.6
Input register reset delay: time between when the
tIRST flip-flop is “reset”(low) and when the output is
consequently “reset” (low)
0.6 0.7 0.9 1.0 1.5 2.0 3.5
tIESU
Input register clock enable setup time: time “enable”
must be stable before the active clock edge
2.3
2.3
2.3
2.3
2.3
2.3
2.3
tIEH
Input register clock enable hold time: time “enable”
must be stable after the active clock edge
0.0
0.0
0.0
0.0
0.0
0.0
0.0
a. These limits are derived from a representative selection of the slowest paths through the QuickRAM logic cell including
typical net delays. Worst case delay values for specific paths should be determined from timing analysis of a particular
design.
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