QL5432-33APQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5432-33APQ208C
QuickLogic Corporation
'QL5432-33APQ208C' PDF : 27 Pages View PDF
QL5432 QuickPCI Data Sheet Rev. C
Architecture Overview
The QL5432 device in the QuickLogic QuickPCI Embedded Standard Product (ESP) family provides a
complete and customizable PCI interface solution combined with programmable logic. This device eliminates
any need for the designer to worry about PCI bus compliance, yet allows for the maximum 32-bit PCI bus
bandwidth (132 MBps).
The programmable logic portion of the device contains 1,417 QuickLogic logic cells and 12 QuickLogic
dual-port RAM blocks. These configurable RAM blocks can be configured in many width/depth
combinations. They can also be combined with logic cells to form FIFOs, or be initialized via Serial EEPROM
on power-up and used as ROMs. See RAM Module Features on page 9 for more information.
The QL5432 device meets PCI v2.2 electrical and timing specifications and has been fully hardware-tested.
The QL5432 device features 3.3 V operation with multi-volt compatible I/Os. Therefore, it can easily
operate in 3 V systems and is fully compatible with 3.3 V, 5 V or Universal PCI card applications.
PCI Controller
The PCI Controller is a 32-bit/33 MHz PCI v2.2 compliant Master/Target Controller. It is capable of infinite
length Master Write and Read transactions at zero-wait-states (132 MBps). The Master will never insert wait-
states during transfers, so data must be supplied or received by FIFOs, which can be configured in the
programmable region of the device. The Master is capable of initiating any type of PCI command, including
configuration cycles and Memory Write and Invalidate (MWI). This enables the QL5432 device to act as a PCI
host. The Master Controller is most often operated by a DMA Controller in the programmable region of the
device. A DMA Controller reference design is available.
The Target interface offers full PCI Configuration Space and flexible target addressing. It supports zero-wait-
state Target write and one-wait-state Target read operations. It also supports retry, disconnect with/without
data transfer, and target abort requested by the backend. Any number of 32-bit BARs may be configured as
memory or I/O space. All required and optional PCI v2.2 Configuration Space registers can be implemented
within the programmable region of the device. A reference design of a Target Configuration and Addressing
module is provided.
The interface ports are divided into a set of ports for Master transactions and a set for Target transactions.
The Master DMA controller and Target Configuration Space and Address Decoding are done in the
programmable logic region of the device. Since these functions are not timing critical, leaving these elements
in the programmable region allows the greatest degree of flexibility to the designer. Reference DMA
controller, Configuration Space, and Address Decoding blocks are included so that the design cycle can be
minimized.
PCI Configuration Space and Address Decode
The configuration space is completely customizable in the programmable region of the device.
PCI address and command decoding is performed by logic in the programmable section of the device. This
allows support for any size of memory or I/O space for backend logic. It also allows the user to implement
any subset of the PCI commands supported by the QL5432. QuickLogic provides a reference Address
Register/Counter and Command Decode block.
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