QL5432-33APQ208C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5432-33APQ208C
QuickLogic Corporation
'QL5432-33APQ208C' PDF : 27 Pages View PDF
QL5432 QuickPCI Data Sheet Rev. C
Internal Port Descriptions
Signals that end with the character 'N' should be considered active-low (for example, Mst_IRDYN). 'I' indicates
that it is an input to the core, 'O' indicates it is an output of the core, and 'B' indicates it is a bi-directional signal
(only on PCI pins).
Master Interface Signals
The master interface signals for QL5432 PCI32N are shown in Table 1.
Table 1: QL5432 PCI32N Master Interface Signals
Signal
PCI_Cmd[3:0]
Mst_Burst_Req
Mst_WrAd[31:0]
Mst_RdAd[31:0]
Mst_WrData[31:0]
Mst_BE[3:0]
Mst_WrData_Valid
Mst_WrData_Rdy
Type
Description
PCI command to be used for the master transaction. This signal must remain
unchanged throughout the period when Mst_Burst_Req is active. PCI commands
considered as reads include:
’0000’ Interrupt Acknowledge
’0010’ I/O Read
’0110’ Memory Read
’1010’ Configuration Read
I
’1100’ Memory Read Multiple
’1110’ Memory Read Line
PCI commands considered as writes include:
’0001’ Special Cycle
’0011’ I/O Write
’0111’ Memory Write
’1011’ Configuration Write
’1111’ Memory Write and Invalidate
Users should make sure that only valid PCI commands are supplied.
Request use of the PCI bus. When it is active, the core requests the PCI bus and once
granted, it generates a master transaction using the command specified by
I PCI_Cmd[3:0]. This signal should be held active until all requested data are transferred
on the PCI bus, and should be deactivated in the second clock cycle following the last
data transfer on PCI (otherwise it is considered as requesting a new transaction).
Address for master DMA writes. This address must always be valid from the beginning
I of a DMA write until the DMA write operation is completed. It should be incremented (by
4 bytes) each time data is transferred on PCI (Mst_Xfer_D1 is active).
Address for master DMA reads. This address must always be valid from the beginning
I
of a DMA read until the DMA read operation is completed. It should be incremented (by
4 bytes) each time data is transferred between the PCI core and the backend
(Mst_RdData_Valid is active).
I Data for master DMA writes (to PCI bus).
I Byte enables for master DMA reads and writes. Active-low.
When this signal is asserted, the core is notified that Mst_WrData[31:0] is valid in master
I write requests. If Mst_BE_Sel is active (high), it also means Mst_BE[3:0] is valid in both
master write/read requests.
Data receives acknowledge from the core for Mst_WrData[31:0] in master write
O
requests, and Mst_BE[3:0] in both write/read requests if Mst_BE_Sel is active (high).
This serves as the PUSH control for the internal FIFO and normally the POP control for
the external FIFO in the backend which provides data and byte enables to the core.
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