QL5632-BPQ208I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5632-BPQ208I
QuickLogic Corporation
'QL5632-BPQ208I' PDF : 34 Pages View PDF
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The 10 QL5632 ECU blocks are placed next to the SRAM circuitry for efficient
memory/instruction fetch and addressing for DSP algorithmic implementations.
Ten 8-bit MAC functions can be implemented per cycle for a total of ~1 billion MACs/s
when clocked at 98 MHz. Additional multiply-accumulate functions can be implemented in
the programmable logic.
The modes for the ECU block are dynamically re-programmable through the programmable
logic.
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00 0
Multiply
7.0 ns max
00 1
Multiply-Add
9.4
ns max
01 0
Accumulateb
4.1 ns 1.2 ns
min
max
01 1
Add
3.3
max
10 0
Multiply (registered)c
10.2 ns 1.2 ns
min
max
1 0 1 Multiply- Add (registered)
10.2 ns 1.2 ns
min
max
1 1 0 Multiply - Accumulate
10.2 ns 1.2 ns
min
max
11 1
Add (registered)
4.1 ns 1.2 ns
min
max
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NOTE: Timing numbers in 7DEOH represent -B Worst Case Commercial conditions.
Instead of requiring extra components, designers simply need to instantiate one of the pre-
configured models (described in this section). The QuickLogic built-in PLLs support a wider
range of frequencies than many other PLLs. These PLLs also have the ability to be cascaded
to support different ranges of frequency multiplications or divisions, driving the device at a
faster or slower rate than the incoming clock frequency. Most importantly, they achieve a
very short clock-to-out time—generally less than 3 ns. This low clock-to-out time is achieved
by the Phase Locked Loop subtracting the clock tree delay through the feedback path,
effectively making the clock tree delay zero.
)LJXUH illustrates a typical QuickLogic ESP PLL.
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