QL5632-BPQ208I View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632-BPQ208I

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

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Quad net

Figure 17: Global Clock Structure

&ORFN

Logic Cells (Internal)

I/O’s (External)

7DEOH  &ORFN 'HOD\

3DUDPHWHUV

&ORFN 3HUIRUPDQFH

*OREDO

'HGLFDWHG

Clock signal generated internally

1.51 ns (max)

n/a

Clock signal generated externally

2.06 ns (max)

1.73 ns (max)

7DEOH  (FOLSVH *OREDO &ORFN 3HUIRUPDQFH

&ORFN 6HJPHQW

3DUDPHWHU

9DOXH QV

0LQ

0D[

tPGCK

Global clock pin delay to quad net

-

tBGCK

Global clock buffer delay (quad net

to flip flop)

-

1.34

0.56



WWWWWW ZZZTXLFNORJLFFRP

Programmable Clock

External Clock

Global Clock Buffer

Global Clock

tPGCK

tBGCK

Figure 18: Global Clock Structure Schematic

Preliminary

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