QL5632-BPT280I View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632-BPT280I

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

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0LQ

tOUTLH Output Delay low to high (90% of H)

-

tOUTHL Output Delay high to low (10% of L)

-

tPZH

Output Delay tri-state to high (90% of H)

-

tPZL

Output Delay tri-state to low (10% of L)

-

tPHZ

Output Delay high to tri-State

-

tPLZ

Output Delay low to tri-State

-

tCOP Clock to out delay (does not include clock tree delays)

-

0D[

0.40

0.55

2.94

2.34

3.07

2.53

3.15 (fast slew)

10.2 (slow slew)

PAD

OUTPUT

REGISTER

Figure 19: Output Register Cell

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Preliminary

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