QL5632 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
QL5632
QuickLogic Corporation
'QL5632' PDF : 34 Pages View PDF
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tIN , tINI
t ICLK
t ISU
+
QE
D
R
-
t SID
PAD
Figure 15: Input Register Cell
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tISU
tIHL
tICLK
tIRST
tIESU
tIEH
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Input register setup time: time the synchronous input of the flip flop must be
stable before the active clock edge
Input register hold time: time the synchronous input of the flip flop must be
stable after the active clock edge
Input register clock to out: time taken by the flip flop to output after the active
clock edge
Input register reset delay: time between when the flip flop is “reset”(low) and
when the output is consequently “reset” (low)
Input register clock enable setup time: time “enable” must be stable before
the active clock edge
Input register clock enable hold time: time “enable” must be stable after the
active clock edge
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3.12
-
0
-
-
1.08
-
0.99
0.37
-
0
-
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