QL6500-7PB516I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL6500-7PB516I' PDF : 73 Pages View PDF
Eclipse Family Data Sheet Rev. F
[9:0]
[17:0]
Figure 22: RAM Module
WA
RE
WD
WE
WCL K
RCLK
[9:0]
RA
[17:0]
RD
ASYNCRD
RAM Module
Table 15: RAM Cell Synchronous Write Timing
Symbol
Parameter
RAM Cell Synchronous Write Timing
tSWA
WA setup time to WCLK: time the WRITE ADDRESS must be stable before the
active edge of the WRITE CLOCK
tHWA
WA hold time to WCLK: time the WRITE ADDRESS must be stable after the
active edge of the WRITE CLOCK
tSWD
WD setup time to WCLK: time the WRITE DATA must be stable before the
active edge of the WRITE CLOCK
tHWD
WD hold time to WCLK: time the WRITE DATA must be stable after the active
edge of the WRITE CLOCK
tSWE
WE setup time to WCLK: time the WRITE ENABLE must be stable before the
active edge of the WRITE CLOCK
tHWE
WE hold time to WCLK: time the WRITE ENABLE must be stable after the
active edge of the WRITE CLOCK
tWCRD
WCLK to RD (WA = RA): time between the active WRITE CLOCK edge and the
time when the data is available at RD
Value
Min.
Max.
0.675 ns
-
0 ns
-
0.654 ns
-
0 ns
-
0.276 ns
-
0 ns
-
-
2.796 ns
24
•
•••
••
www.quicklogic.com
© 2007 QuickLogic Corporation
Share Link: 
