QL6500-7PB516I View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL6500-7PB516I' PDF : 73 Pages View PDF
Eclipse Family Data Sheet Rev. F
Table 18: Standard Input Delays
Symbol
tSID (LVTTL)
tSID (LVCMOS2)
tSID (GTL+)
tSID (SSTL3)
tSID (SSTL2)
Parameter
To get the total input delay add this delay to tISU
LVTTL input delay: Low Voltage TTL for 3.3 V applications
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower applications
GTL+ input delay: Gunning Transceiver Logic
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V
Figure 27: Eclipse Input Register Cell Timing
R
Value
Min. Max.
- 0.34 ns
- 0.42 ns
- 0.68 ns
- 0.55 ns
- 0.61 ns
CLK
D
tISU
tIHL
Q
tICO
tIRST
E
tIESU
tIEH
28
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