QL7120_02 View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL7120_02' PDF : 41 Pages View PDF
4/ (FOLSVH3OXV 'DWD 6KHHW 5HY $
6\PERO
tISU
tIHL
tICO
tIRST
tIESU
tIEH
7DEOH ,QSXW 5HJLVWHU &HOO
3DUDPHWHU ,QSXW 5HJLVWHU &HOO 2QO\
9DOXH
0LQ 0D[
Input register setup time: the time the synchronous input of the flip-flop must be
stable before the active clock edge
3.12 ns
-
Input register hold time: the time the synchronous input of the flip-flop must be
stable after the active clock edge
0 ns
-
Input register clock-to-out: the time taken by the flip-flop to output after the active
clock edge
- 1.08 ns
Input register reset delay: the time between when the flip-flop is “reset”(low) and
when the output is consequently “reset” (low)
- 0.99 ns
Input register clock enable setup time: the time “enable” must be stable before the
active clock edge
0.37 ns
-
Input register clock enable hold time: the time “enable” must be stable after the
active clock edge
0 ns
-
7DEOH 6WDQGDUG ,QSXW 'HOD\V
6\PERO
3DUDPHWHU
6WDQGDUG ,QSXW 'HOD\V
7R JHW WKH WRWDO LQSXW GHOD\ DGG WKLV GHOD\ WR W,68
tSID (LVTTL)
tSID (LVCMOS2)
LVTTL input delay: Low Voltage TTL for 3.3 V applications
LVCMOS2 input delay: Low Voltage CMOS for 2.5 V and lower
applications
tSID (GTL+)
tSID (SSTL3)
tSID (SSTL2)
GTL+ input delay: Gunning Transceiver Logic
SSTL3 input delay: Stub Series Terminated Logic for 3.3 V
SSTL2 input delay: Stub Series Terminated Logic for 2.5 V
9DOXH
0LQ 0D[
- 0.34 ns
- 0.42 ns
- 0.68 ns
- 0.55 ns
- 0.61 ns
R
CLK
D
tISU
t IHL
Q
tICO
t IRS T
E
tIESU tIEH
)LJXUH (FOLSVH3OXV ,QSXW 5HJLVWHU &HOO 7LPLQJ
WWWWWW ZZZTXLFNORJLFFRP
4XLFN/RJLF &RUSRUDWLRQ
Share Link: 
