QL901M-6PS680C View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL901M-6PS680C' PDF : 37 Pages View PDF
Table 22: QuickMIPS Interface Port Synchronous Timing (to hclk) (Continued)
Setup Time (Tsu)
Hold Time (Thold)
Clock-to-out Time (Tco)
ahbm_hburst
10.79
0
X
ahbm_hprotb
–
–
X
ahbm_hwdata
10.39
0
X
ahbm_hrdata
X
X
16.28
ahb_hready_in
X
X
11.82
ahbm_hresp
X
X
9.02
ahbm_hbusreq
7.40
0
X
ahbm_hgrant
X
X
16.64
Fabric APB Slave Ports
apbs_paddr
X
X
4.52
apbs_pwdata
X
X
4.66
apbs_penable
X
X
2.87
apbs_pwrite
X
X
4.13
apbs_psel0
X
X
3.80
apbs_psel1
X
X
3.43
apbs_psel2
X
X
3.25
apbs_prdata0
7.44
0
X
apbs_prdata1
6.79
0
X
apbs_prdata2
6.97
0
X
Timer Ports
tm_fbenable
0.23
0
X
tm_overflow2
X
X
4.35
tm_overflow3
X
X
4.48
tm_overflow4
X
X
5.00
(Sheet 2 of 2)
a. “x” indicates that this timing delay does not apply to the signal.
b. The ahbm_hprot signal is NOT used by any slave within the standard cell part of the chip. None of the mas-
ters besides the processor-AHB-bridge generates this signal. Therefore there is no setup or hold timing for
ahbm_hprot.
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