Macro
I/O
Skew
Figure 8: QuickMIPS Global Clock Structure
Table 6: QuickMIPS Clock Performance
Clock Performance
Global
Dedicated
1.51 ns
2.06 ns
0.55 ns
1.59 ns
1.73 ns
0.14 ns
Table 7: QuickMIPS Input Register Cell
Symbol
Input Register Cell Only
Parameter
tGCKP
Global clock pin delay to quad net
GCKB
Global clock buffer delay (quad net to flip flop)
Propagation delay (ns)
1.34
0.56
Programmable Clock
Hardware Clock
Global Clock Buffer
Global Clock
tPGCK
tBGCK
Figure 9: Global Clock Structure Schematic
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