QL901M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL901M' PDF : 37 Pages View PDF
[9:0]
[17:0]
[1:0]
WA
RE
WD
WE
WCL K
MOD E
RCLK
[9:0]
RA
[17:0]
RD
ASYNCRD
QuickRAM Module
Figure 10: RAM Module
Table 8: RAM Cell Synchronous Write Timing
Symbol
Parameter
RAM Cell Synchronous Write Timing
tSWA
WA setup time to WCLK: the amount of time the WRITE ADDRESS must be
stable before the active edge of the WRITE CLOCK
tHWA
WA hold time to WCLK: the amount of time the WRITE ADDRESS must be
stable after the active edge of the WRITE CLOCK
tSWD
WD setup time to WCLK: the amount of time the WRITE DATA must be stable
before the active edge of the WRITE CLOCK
tHWD
WD hold time to WCLK: the amount of time the WRITE DATA must be stable
after the active edge of the WRITE CLOCK
tSWE
WE setup time to WCLK: the amount of time the WRITE ENABLE must be
stable before the active edge of the WRITE CLOCK
tHWE
WE hold time to WCLK: the amount of time the WRITE ENABLE must be stable
after the active edge of the WRITE CLOCK
tWCRD
WCLK to RD (WA=RA): the amount of time between the active WRITE CLOCK
edge and the time when the data is available at RD
Propagation
delay (ns)
0.675
0
0.654
0
0.623
0
4.38
QL901M QuickMIPS™ Data Sheet Rev B
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