QL901M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL901M' PDF : 37 Pages View PDF
WCLK
WA
tSWA
tHWA
WD
tSWD
tHWD
WE
tSWE
tHWE
RD
old data
new data
tWCRD
Figure 11: RAM Cell Synchronous Write Timing
Table 9: RAM Cell Synchronous & Asynchronous Read Timing
Symbol
Parameter
RAM Cell Synchronous Read Timing
Propagation
delay (ns)
tSRA
RA setup time to RCLK: the amount of time the READ ADDRESS must
be stable before the active edge of the READ CLOCK
0.686
tHRA
RA hold time to RCLK: the amount of time the READ ADDRESS must
be stable after the active edge of the READ CLOCK
0
tSRE
RE setup time to WCLK: the amount of time the READ ENABLE must be
stable before the active edge of the READ CLOCK
0.243
tHRE
RE hold time to WCLK: the amount of time the READ ENABLE must be
stable after the active edge of the READ CLOCK
0
tRCRD
RCLK to RD: the amount of time between the active READ CLOCK edge
and the time when the data is available at RD
4.38
RAM Cell Asynchronous Read Timing
rPDRD
RA to RD: amount of time between when the READ ADDRESS is input
and when the DATA is output
2.06
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12
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