QL901M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL901M' PDF : 37 Pages View PDF
tIN, tINI
tICLK
tISU
+
-
QE
D
R
tSID
PAD
Figure 14: QuickMIPS Input Register Cell
Table 10: Input Register Cell
Symbol
Input Register Cell Only
Parameter
Propagation
delay (ns)
tISU
Input register setup time: the amount of time the synchronous input of
the flip flop must be stable before the active clock edge
3.12
tIH
Input register hold time: the amount of time the synchronous input of the
flip flop must be stable after the active clock edge
0
tICLK
Input register clock to Q: the amount of time taken by the flip flop to
output after the active clock edge
1.08
tIRST
Input register reset delay: amount of time between when the flip flop is
“reset”(low) and when Q is consequently “reset” (low)
0.99
tIESU
Input register clock enable setup time: the amount of time “enable” must
be stable before the active clock edge
0.37
tIEH
Input register clock enable time: the amount of time “enable” must be
stable after the active clock edge
0
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