QL901M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL901M' PDF : 37 Pages View PDF
RXCLK(in)
RXDV(in)
RXER(in)
tdv_h
ter_h
tdv_s
ter_s
RXD[3:0](in)
tdata_s
tdata_h
Figure 20: Ethernet MAC Receive Interface Waveforms
Table 18: Ethernet MAC Receive Interface AC Timing
Parameter
Min
Max
Units
tdv_s
RXDV (receive data valid) to RXCLK setup time
2.0
ns
tdv_h
RXDV (receive data valid) from RXCLK hold time
2.0
ns
ter_s
RXER (receive data error) to RXCLK setup time
2.0
ns
ter_h
RXER (receive data error) from RXCLK hold time
2.0
ns
tdata_s
RXD (receive data) to RXCLK setup time
2.0
ns
tdata_h
RXD (receive data) from RXCLK hold time
2.0
ns
The timing of the MII Management Interface listed below depends on the system clock frequency. The
numbers displayed are correct for a processor clock frequency of 100 MHz and an AMBA bus system
clock frequency of 50 MHz. Note that for a system clock of 133 MHz, the mandatory MDC minimum
clock cycle of 400ns for some PHY devices will not be met.
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