QL901M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL901M' PDF : 37 Pages View PDF
Tcyc
Thigh
Tlow
–
Tval
Tval (ptp)
Ton
Toff
Tsu
Tsu (ptp)
Th
Trst
Trst-clk
Trst-offc
Trhfa
Trhff
Table 16: PCI AC Timing
Parametera
66 MHz
Min
Max
PCI_CLK Cycle Time
15
PCI_CLK High Time
6
PCI_CLK Low Time
6
PCI_CLK Slew Rate
1.5
4
PCI_CLK to Signal Valid Delay
2
6
PCI_CLK to Signal Valid Delay
point-to-point signalsb
2
6
Float to Active Delay
2
Active to Float Delay
14
Input Setup Time to PCI_CLK
bused signals
3
Input Setup Time to PCI_CLK
point-to-point
5
Input Hold Time from PCI_CLK
0
Reset Active Time after power stable
1
Reset Active Time after PCI_CLK stable
100
Reset Active to output float delay
40
PCI_RST_n high to first configuration access
2
PCI_RST_n high to first PCI_FRAME_n assertion
5
33 MHz
Min
Max
30
11
11
1
4
2
11
2
12
2
28
7
10, 12
0
1
100
40
2
5
a. All PCI pins are synchronous to the PCI clock except for PCI_RST_n and PCI_INTA_n.
b. Point-to-point signals include PCI_REQ_n and PCI_GNT_n.
c. All output drivers must be 3-stated when PCI_RST_n is active.
Units
ns
ns
ns
V/ns
ns
ns
ns
ns
ns
ns
ns
ms
µs
ns
clocks
clocks
ten_c2q
tdata_v
tdata_h
TXCLK(in)
TXEN(out)
TXD[3:0](out)
ten_c2q
tdata_h
tdata_v
Figure 19: Ethernet MAC Transmit Interface Waveforms
Table 17: Ethernet MAC Transmit Interface AC Timing
Parameter
Min
Max
Time from the rising clock edge of TXCLK to
the change in TXEN
8.0
Time from the rising clock edge of TXCLK to all
data signals having valid stable values
9.0
Time in which the output data is still valid after
the rising clock edge of TXCLK
0.0
QL901M QuickMIPS™ Data Sheet Rev B
Units
ns
ns
ns
•
••
19
•
••
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