QL901M View Datasheet(PDF) - QuickLogic Corporation
Part Name
Description
MFG CO.
'QL901M' PDF : 37 Pages View PDF
SD_CLKIN
ADDR[23:0]
SD_CS_n[3:0]
SD_CKE[3:0]
SD_DQM[3:0]
SD_RAS_n
SD_CAS_n
SD_WE_n
DATA(output)[31:0]
DATA(input[31:0]
Tco_sdram
Tsu_sdram
Th_sdram
Figure 23: SDRAM Waveforms
Table 21: SDRAM AC Timing
Parametera
Min
Max
Units
Tco
DATA, ADDR, SD_RAS_n, SD_CAS_n, SD_CS_n[3:0],
SD_DQM[3:0], SD_WE_n, SD_CKE[3:0]
2
8
ns
Tsu
DATA
12
ns
Th
DATA
2
ns
a. All timing is measured with respect to the rising edge of SD_CLKIN. All measurements are based on I/Os with 35 pF
load except for SD_CLKOUT, which has a load of 15 pF.
Internal_AHB_Clock
CS_n
ADDR[31:0]
BLS_n[3:0]
OEN_n
WEN_n
DATA[31:0]
addr
byte lane select
D0
D1
read data
Figure 24: SRAM Read Waveforms
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