Intel£ Advanced+ Boot Block Flash Memory (C3)
Table 19. Write Operations—32 Mbit Density
Density
32 Mbit
# Sym
Parameter
Product
3.0 V – 3.6 V6
VCC
2.7 V – 3.6 V
70 ns
70
90 ns
90
100 ns
90
100
110 ns
100
Unit
110
Note Min
Min
Min
Min
Min Min
W1
tPHWL / RP# High Recovery to WE# (CE#)
tPHEL Going Low
4,5
150 150
150
150
150 150 ns
W2
tELWL / CE# (WE#) Setup to WE# (CE#)
tWLEL Going Low
4,5
0
0
0
0
0
0
ns
tWLWH
W3 /
WE# (CE#) Pulse Width
tELEH
1,4,5 45
60
60
70
70
70 ns
W4
tDVWH /
tDVEH
Data Setup to WE# (CE#) Going High
2,4,5
40
40
50
60
60
60 ns
W5
tAVWH / Address Setup to WE# (CE#) Going
tAVEH High
2,4,5
50
60
60
70
70
70 ns
W6
tWHEH / CE# (WE#) Hold Time from WE#
tEHWH (CE#) High
4,5
0
0
0
0
0
0
ns
W7
tWHDX / Data Hold Time from WE# (CE#)
tEHDX High
2,4,5
0
0
0
0
0
0
ns
W8
tWHAX / Address Hold Time from WE# (CE#)
tEHAX High
2,4,5
0
0
0
0
0
0
ns
W9
tWHWL /
tEHEL
WE# (CE#) Pulse Width High
1,4,5 25
30
30
30
30
30 ns
W10
tVPWH /
tVPEH
VPP Setup to WE# (CE#) Going High
3,4,5
200
200
200
200
200 200 ns
W11 tQVVL VPP Hold from Valid SRD
3,4
0
0
0
0
0
0
ns
W12
tBHWH /
tBHEH
WP# Setup to WE# (CE#) Going
High
3,4
0
0
0
0
0
0
ns
W13 tQVBL WP# Hold from Valid SRD
3,4
0
0
0
0
0
0
ns
W14 tWHGL WE# High to OE# Going Low
3,4
30
30
30
30
30
30 ns
NOTES:
1. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high (whichever
goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH. Similarly, write pulse width high (tWPH) is defined from CE# or
WE# going high (whichever goes high first) to CE# or WE# going low (whichever goes low last). Hence,
tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
2. Refer to Table 7, “Command Bus Operations” on page 24 for valid AIN or DIN.
3. Sampled, but not 100% tested.
4. See Figure 11, “AC Input/Output Reference Waveform” on page 49 for timing measurements and maximum allowable input
slew rate.
5. See Figure 9, “Write Operations Waveform” on page 47.
6. VCCMax = 3.3 V for 32-Mbit 0.25 Micron product.
Datasheet
45