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RS8953SPBEPF View Datasheet(PDF) - Conexant Systems

Part Name
Description
MFG CO.
RS8953SPBEPF
Conexant
Conexant Systems Conexant
'RS8953SPBEPF' PDF : 173 Pages View PDF
RS8953B/8953SPB
HDSL Channel Unit
0xF4—Command Register 7 (CMD_7)
4.0 Registers
4.11 Common Command
7
PRA_EN
6
5
FEBE_POLARITY NCO_SCALE
4
RCLK_INV
3
2
PHD_MODE
1
FAST_ACQ
0
DPLL_ERR_EN
DPLL_ERR_EN
FAST_ACQ
PHD_MODE
RCLK_INV
DPLL Error Interrupt Enable—Enables DPLL errors to request RX_ERR interrupt when an
overflow or underflow condition occurs at the phase detector output. DPLL errors are latched
and reported in ERR_STATUS [addr 0x3C] regardless of DPLL_ERR_EN.
0 = DPLL errors do not generate a RX_ERR interrupt
1 = DPLL errors generate a RX_ERR interrupt
Fast Acquisition—Enables DPLL fast frequency acquisition by instructing the NCO to reuse
the residual phase calculated prior to a DPLL error condition. The phase detector initializes
according to PHD_MODE (see below) while the NCO continues tracking the last known
phase, thus widening the DPLL bandwidth. FAST_ACQ is preferable while the master framer
remains IN_SYNC. To avoid RCLK frequency violations, FAST_ACQ may be disabled when
the master framer is OUT_OF_SYNC.
0 = Disable fast acquisition
1 = Enable fast acquisition
NOTE: If the system determines that the DPLL is not locked, then the MPU must assert
DPLL _RST [addr 0xF6] to force the DPLL to reload DPLL_RSID [addr 0xD5]. The
system may monitor DPLL tracking by reading RESID_OUT [addr 0x28] or by
checking DPLL_ERR [ERR_STATUS; addr 0x3C].
Phase Detector Init Mode—Selects a method to initialize the phase detector window when a
DPLL error occurs. The phase detector can either initialize to the center of the phase window
or opposing edge, not initialize at all, or use the programmed DPLL_PINI [addr 0xDB] value.
PHD_MODE
00
01
10
11
Phase Detector Initialization
DPLL_PINI value
Opposing edge of phase window
Disabled (infinite phase window)
Center of phase window
NOTE: Disabling the phase detector is not recommended as the error output can remain
saturated without reporting the DPLL error status or generating DPLL interrupts.
Receive Output Clock Inverted—Enables binary inversion of the clock selected by
RCLK_SEL [CMD_2; addr 0xE6].
0
RCLK = Clock selected by RCLK_SEL
1
RCLK = Inverted clock selected by RCLK_SEL
N8953BDSB
Conexant
4-49
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