RS8953B/8953SPB
HDSL Channel Unit
4.0 Registers
4.17 PRA Receive Read
4.17 PRA Receive Read
Table 4-14. PRA Receive Read Registers
Address
Register Label
0x80
RX_PRA_CTRL0
0x81
RX_PRA_CTRL1
0x82
RX_BITS_BUFF1
0x83
RX_PRA_E_CNT
0x84
RX_PRA_CRC_CNT
0x85
RX_PRA_CODE
0x86
RX_PRA_MON0
0x87
RX_PRA_MON2
Bits
Name/Description
7
PRA Receive Read Register 0
8
PRA Receive Control Register 1
8
PRA Receive Bits Buffer 1
8
PRA Receive E Bit Counter
8
PRA Receive CRC4 Error Counter
6
PRA Receive In-Band Code
6
PRA Receive Monitor Register 0
4
PRA Receive Monitor Register 2
0x80—PRA Receive Control Register 0 (RX_PRA_CTRL0)
7
6
E_MODE[1:0]
5
4
3
2
1
SA8_MODE
SA7_MODE
—
SA6_MODE
SA5_MODE
SA4_MODE
SA5_MODE
SA6_MODE
SA7_MODE
SA8_MODE
Controls the behavior of Sa4 bits transmitted towards PCM, as follows:
0 = Transparent
1 = From bits buffer 1
Controls the behavior of Sa5 bits transmitted towards PCM, as follows:
0 = Transparent
1 = From bits buffer 1
Controls the behavior of Sa6 bits transmitted towards PCM, as follows:
0 = Transparent
1 = From bits buffer 0
Controls the behavior of Sa7 bits transmitted towards PCM, as follows:
0 = Transparent
1 = From bits buffer 1
Controls the behavior of Sa8 bits transmitted towards PCM, as follows:
0 = Transparent
1 = From bits buffer 1
0
SA4_MODE
N8953BDSB
Conexant
4-73