RS8953B/8953SPB
HDSL Channel Unit
3.0 Circuit Descriptions
3.2 PCM Channel
Figure 3-10. PCM Receive Data Timing
HDSL 6ms
Master
PCM 6ms
RMSYNC
RSER
Bit
RSER
Frame
RSER
Mframe
RFIFO_WL = PCM Bit Delay
1 2 3 M RFRAME_LOC[M] = RMSYNC Bit Delay
12 345 6N
RMF_LOC[N] = RMSYNC Frame Delay
FRAME_LEN[X] = PCM Frame Length
0
X
Frame 0
Frame Y
MF_LEN[Y] = PCM Multiframe Length
MF_CNT[Z] = PCM Mframes per 6 ms period
Mframe 0
Mframe Z
NOTE(S): RMSYNC can mark any RSER bit position by programming RFAME_LOC and RMF_LOC.
N8953BDSB
Conexant
3-11