RS8953SPBEPF View Datasheet(PDF) - Conexant Systems
Part Name
Description
MFG CO.
'RS8953SPBEPF' PDF : 173 Pages View PDF
RS8953B/8953SPB
HDSL Channel Unit
3.0 Circuit Descriptions
3.3 Clock Recovery DPLL
3.3 Clock Recovery DPLL
The Digital Phase Locked Loop (DPLL) shown in Figure 3-14 synthesizes the
PCM Receive Clock (RCLK) from a 60–80 MHz High Frequency Clock
(HFCLK). HFCLK is developed by analog PLL multiplication of the MCLK
input frequency, or HFCLK is applied directly to the MCLK input (see
PLL_MUL and PLL_DIS in CMD_1; addr 0xE5). The analog PLL requires
external loop filter components and connections as shown in Figure 6-1. HFCLK
must be in the range of 60–80 MHz, but requires no specific frequency or phase
relationship to PCM or HDSL clocks. Open or closed loop operation is selected
by DPLL_NCO [CMD_5; addr E9].
Figure 3-14. DPLL Block Diagram
MCLK
PLL
x PLL_MUL
÷4
~ 15-20 MHz
HFCLK ~ 60-80 MHz
PLL_DIS
÷ PLL_DIV
GCLK ~ 12 MHz
Phase Detector
CH1 RSYNC
CH2 RSYNC
CH3 RSYNC
MASTER_SEL
HDSL 6ms
PCM 6ms
CNT
Start
Stop
RST
DPLL_RST
DPLL Filter
DPLL_GAIN
Z-1
DPLL_NCO
INIT
÷ MF_CNT
÷ MF_LEN
NCO
DPLL_FACTOR
÷ N-1
÷N
÷ N+1
÷2
÷N
÷ N+1
÷ N+2
SUM
Z-1 OVF
DPLL_RESID
÷ FRAME_LEN
SCLK
RCLK
N8953BDSB
Conexant
3-15
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