S9S08LG16J0VLF View Datasheet(PDF) - Freescale Semiconductor
Part Name
Description
MFG CO.
'S9S08LG16J0VLF' PDF : 50 Pages View PDF
2.11 AC Characteristics
This section describes timing characteristics for each peripheral system.
Electrical Characteristics
2.11.1 Control Timing
Table 14. Control Timing
Num C
Rating
Symbol
Min
Typ1
Max Unit
1
D Bus frequency (tcyc = 1/fBus)
fBus
dc
—
20
MHz
2 D Internal low power oscillator period
3 D External reset pulse width2
tLPO
700
textrst
100
—
1300 μs
—
—
ns
4 D Reset low drive
trstdrv
66 x tcyc
—
—
ns
5 D BKGD/MS setup time after issuing background debug tMSSU
500
force reset to enter user or BDM modes
—
—
ns
6 D BKGD/MS hold time after issuing background debug
tMSH
100
force reset to enter user or BDM modes 3
—
—
μs
7 D IRQ pulse width
Asynchronous path2
Synchronous path4
tILIH
100
—
tIHIL
1.5 x tcyc
—
ns
—
—
8 D Keyboard interrupt pulse width
Asynchronous path2
Synchronous path4
tILIH
100
—
tIHIL
1.5 x tcyc
—
ns
—
—
9
C Port rise and fall time — (load = 50 pF)5, 6
ns
Slew rate control disabled (PTxSE = 0)
Slew rate control enabled (PTxSE = 1)
tRise
—
tFall
—
3
—
30
—
1 Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
2 This is the shortest pulse that is guaranteed to be recognized as a reset pin request.
3 To enter BDM mode following a POR, BKGD/MS should be held low during the power-up and for a hold time of tMSH after VDD
rises above VLVD.
4 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or
may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized.
5 Timing is shown with respect to 20% VDD and 80% VDD levels. Temperature range –40 °C to 105 °C.
6 Except for LCD pins in Open Drain mode.
RESET PIN
textrst
Figure 19. Reset Timing
MC9S08LG32 Series Data Sheet, Rev. 7
Freescale Semiconductor
29
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