SC120 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC120' PDF : 32 Pages View PDF
SC120
Applications Information (continued)
PWM Operation
The PWM cycle runs at a fixed frequency (f = 1.2MHz),
osc
with a variable duty cycle (D). PWM operation continually
draws current from the input supply (except for discon-
tinuous mode, described subsequently). During the on-
state of the PWM cycle, the n-channel FET is turned on,
grounding the inductor at the LX pin. This causes the
current flowing from the input supply through the induc-
tor to ground to ramp up. During the off-state, the n-
channel FET is turned off and the p-channel FET
(synchronous rectifier) is turned on. This causes the
inductor current to flow from the input supply through
the inductor into the output capacitor and load, boosting
the output voltage above the input voltage. The cycle
then repeats to re-energize the inductor.
Ideally, the steady state (constant load) duty cycle is
determined by D = 1 – (VIN/VOUT), but must be greater in
practice to overcome dissipative losses. The SC120 PWM
controller constrains the value of D such that 0.15 < D < 0.90
(approximately).
The average inductor current during the off-state multi-
plied by (1-D) is equal to the average load current. The
inductor current is alternately ramping up (on-state) and
down (off-state) at a rate and amplitude determined by
the inductance value, the input voltage, and the on-time
(T = D×T, T = 1/f ). Therefore, the instantaneous induc-
ON
OSC
tor current will be alternately larger and smaller than the
average. If the average output current is sufficiently small,
the minimum inductor current can reach zero during the
off-state. If the energy stored in the inductor is depleted
(the inductor current decreases to zero) during the off-
state, both FETs turn off for the remainder of the off-state.
If this discontinuous mode (DM) operation persists, the
SC120 transitions to PSAVE operation.
PSAVE Operation
At light loads, the SC120 will operate in PSAVE mode. At
low output load, PSAVE mode will operate more efficiently
than PWM mode. PSAVE mode also ensures regulation
while the output load is too small to keep the PWM mode
duty cycle above its minimum value, especially when V
IN
is close to V . PSAVE operation is triggered by 256 con-
OUT
secutive cycles of DM operation in PWM mode, when the
output of the P amplifier falls to 0V during the off-state
LIM
due to low load current.
PSAVE mode requires fewer circuit resources than PWM
mode. All unused circuitry is disabled to reduce quies-
cent power dissipation. In PSAVE mode, the OUT pin
voltage monitoring circuit remains active and the output
voltage error amplifier operates as a comparator. PSAVE
regulation is shown in Figure 2. When V < 1.008xV ,
OUT
REG
where V is the programmed output voltage, a burst of
REG
fixed-period switching occurs to boost the output voltage.
The n-channel FET turns on (on-state) until the inductor
current rises to approximately 240mA. The n-channel FET
then turns off and the p-channel FET turns on to transfer
the inductor energy to the output capacitor and load for
the duration of the off-state. This cycle repeats until
VOUT > 1.018×VREG, at which point both FETs are turned off.
The output capacitor then discharges into the load until
V < 1.008×V , and the burst cycle repeats.
OUT
REG
When the output current increases above a predeter-
mined level, either of two PSAVE exit conditions will force
the resumption of PWM operation. The first PSAVE exit
criterion is shown in Figure 2. If the PSAVE burst cycle
cannot provide sufficient current to the output, the
output voltage will decrease during the burst. If
V < 0.98 × V , PWM operation will resume. The second
OUT
REG
PSAVE exit criterion, illustrated in Figure 3, depends on
the rate of discharge of the output capacitor between
PSAVE bursts. If the time between bursts is less than 5μs,
then PWM operation resumes. The output capacitance
value will affect the second criterion, but not the first.
Reducing the output capacitor will reduce the output
load at which PSAVE mode exits to PWM mode.
Within each on/off cycle of a PSAVE burst, the rate of
decrease of the inductor current during the off-state is
proportional to (V − V ). If V is sufficiently close to
OUT
IN
IN
V , the decrease in current during the off-state may not
OUT
overcome the increase in current during the minimum
on-time of the on-state, approximately 100ns. This can
result in the peak inductor current rising above the PSAVE
mode n-channel FET current limit. (Normally, when the
n-channel FET current limit is reached, the on-state ends
immediately and the off-state begins. This sets the duty
cycle on a cycle-by-cycle basis.) This inductor current rise
21
Share Link: 
