SC120
Applications Information (continued)
³ 'ILon
1 DT
L 0 VIN dt
VIN uD u T
L
This is the change in I during the on-state. During the
L
off-state, again neglecting the p-channel FET R and
DS-ON
the inductor DCR,
³ 'ILoff
1
L
T
VIN VOUT
DT
dt
VIN VOUT u T 1 D
L
Note that this is a negative quantity, since V > V and
OUT
IN
0 < D < 1. For a constant load in steady-state, the inductor
current must satisfy ΔI + ΔI = 0. Substituting the two
L-on
L-off
expressions and solving for D, obtain D = 1 – V /V .
IN OUT
Using this expression, and the positive valued expression
ΔI = ΔI for current ripple amplitude, obtain expanded
L
L-on
expression for I and I .
L-max
L-min
ILmax,min
VOUT uIOUT
VIN u K
r T u VIN
2 u L VOUT
u
VOUT
VIN
If the value of IOUT decreases until IL-min = 0, which is the
boundary of continuous and discontinuous PWM opera-
tion, the SC120 will transition from PWM operation to
PSAVE operation. Define this value of IOUT as I . PSAVE-entry
Setting the expression for I to 0 and solving,
L-min
IPSAVEentry
K
2
u
u
T
L
¨¨©§
VIN
VOUT
¸¸¹·2
VOUT
VIN
The programmed value of V is constant. I
is a
OUT
PSAVE-entry
polynomial function of V . Equating dI
/dV = 0
IN
PSAVE-entry IN
and solving for V reveals that there is one non-zero extre-
IN
mum of this function, a maximum, at V = 2/ V .*
IN
3 OUT
Applying this value of V ,
IN
IPSAVE entry max
K
u
L
T
u
2
27
u
VOUT
The value of the inductor determines the PSAVE entry
output load current for a given V . Evaluate I
at the
IN
PSAVE-entry
* For simplicity, efficiency (η) is represented as a constant. But efficien-
cy, itself a function of V , decreases with decreasing V (and decreases
IN
IN
with increasing temperature). Therefore at a given temperature, the
input voltage that produces the maximum PSAVE entry load current
will be slightly greater than 2/ of V .
3
OUT
smallest and largest expected values of V . If the input
IN
range
includes
V
IN
=
2/3
V,
OUT
also
determine
I
.
PSAVE-entry-max
Note that at high V (V close to V ) PSAVE exit may
IN IN
OUT
require an unusually high output load current. In this
case, PSAVE re-entry may be of little concern. So if the
largest V exceeds approximately 90% of V , instead
IN
OUT
evaluate PSAVE entry at V = 0.9V .
IN
OUT
To ensure that I
will be less than the PSAVE exit
PSAVE-entry-max
current, evaluate the PSAVE-PWM mode transistions while
applying increasing and decreasing loads with VIN at and
above
2/3
V.
OUT
This should be done at the application’s
lowest specified ambient temperature as well as at room
temperature. If the PSAVE exit current is not sufficiently
greater than the PSAVE entry current, the separation can
be enhanced by increasing the output capacitance to raise
IPSAVE-exit due to the 5μs off-time criterion (see Figure 3), or
by increasing the inductor value to reduce I
.
PSAVE-entry
The inductor selection should also consider the n-channel
FET current limit for the expected range of input voltage
and output load current. The largest I will occur at the
L-avg
expected smallest V and largest I . Determine the
IN
OUT
largest allowable ΔI , based on the largest expected I ,
L
L-avg
the minimum n-channel FET current limit, and the
inductor tolerance. Ensure that in the worst case,
I + ΔI /2 < I .
L-avg
L
LIM(N)
These calculations include the parameter η, efficiency.
Efficiency varies with V , I , and temperature.
IN OUT
Estimate η
using the plots provided in this datasheet, or from experi-
mental data, at the operating condition of interest when
computing the effect of a new inductor value on PSAVE
entry and I-limit margin.
Any chosen inductor should have low DCR, compared to
the R of the FET switches, to maintain efficiency,
DS-ON
though for DCR << R , further reduction in DCR will
DS-ON
provide diminishing benefit. The inductor I value should
SAT
exceed the expected I . The inductor self-resonant fre-
L-max
quency should exceed 5×f . Any inductor with these
osc
properties should provide satisfactory performance.
L = 4.7μH should perform well for most applications. For
high VOUT, (4.0V to 5.0V), and relatively high VIN (3.3V and
above), L = 6.8μH, along with a larger output capacitance
or larger-package output capacitor (for better V-bias per-
25