SC173AMLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
SC173AMLTRT
Semtech Corporation
'SC173AMLTRT' PDF : 26 Pages View PDF
SC173A
inductor current flows through it and creates a voltage
across the RDS(ON). During this time, the voltage across the
MOSFET is negative with respect to ground. During this
time, If this MOSFET voltage drop exceeds the internal
reference voltage, the current limit will activate. The cur-
rent limit then keeps the low-side MOSFET on and will
not allow another high side on-time, until the current in
the low-side MOSFET reduces enough to drop below the
internal reference voltage once more. This method regu-
lates the inductor valley current at the level shown by ILIM
in Figure 5.
IPEAK
ILOAD
ILIM
Time
Figure 5 — Valley Current Limit
Setting the valley current limit to a value of ILIM results
in a peak inductor current of ILIM plus the peak-to-peak
ripple current. In this situation, the average (load) current
through the inductor will be ILIM plus one half the peak-
to-peak ripple current.
Soft start of PWM Regulator
Soft start is achieved in the PWM regulator by using
an internal voltage ramp as the reference for the FB
comparator. The voltage ramp is generated using an
internal charge pump which drives the reference from
zero to 750mV in ~1.8mV increments, using an internal
~500kHz oscillator. When the ramp voltage reaches
750mV, the ramp is ignored and the FB comparator
switches over to a fixed 750mV threshold. During soft start
the output voltage tracks the internal ramp, which limits
the start-up inrush current and provides a controlled soft
start profile for a wide range of applications. Typical soft
start ramp time is 0.85ms.
© 2010 Semtech Corporation
During soft start the regulator turns off the low-side
MOSFET on any cycle if the inductor current falls to zero.
This prevents negative inductor current, allowing the
device to start into a pre-biased output.
Power Good Output
The power good (PGOOD) output is an open-drain output
which requires a pull-up resistor. When the output volt-
age is 10% below the nominal voltage, PGOOD is pulled
low. It is held low until the output voltage returns to the
nominal voltage. PGOOD is held low during soft start and
activated approximately 1ms after VOUT reaches regula-
tion. The total PGOOD delay is typically 2ms.
PGOOD will transition low if the VFB pin exceeds +20% of
nominal, which is also the over-voltage shutdown thresh-
old (900mV). PGOOD also pulls low if the EN pin is low
when VDD is present.
Output Over-Voltage Protection
Over-Voltage Protection (OVP) becomes active as soon
as the device is enabled. The threshold is set at 750mV +
20% (900mV). When VFB exceeds the OVP threshold, DL
latches high and the low-side MOSFET is turned on. DL
remains high and the controller remains off, until the EN
input is toggled or VDD is cycled. There is a 5μs delay built
into the OVP detector to prevent false transitions. PGOOD
is also low after an OVP event.
Output Under-Voltage Protection
When VFB falls to 75% of its nominal voltage (falls to
562.5mV) for eight consecutive clock cycles, the switcher
is shut off and the DH and DL drives are pulled low to turn
off the MOSFETs. The controller stays off until EN is tog-
gled or VDD is cycled.
VDD UVLO, and POR
Under-Voltage Lock-Out (UVLO) circuitry inhibits switch-
ing and tri-states the power FETs until VDD rises above
2.9V. An internal Power-On Reset (POR) occurs when VDD
exceeds 2.9V, which resets the fault latch and soft start
counter to begin the soft start cycle. The SC173A then
begins a soft start cycle. The PWM will shut off if VDD falls
below 2.7V.
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