SC2000 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SC2000' PDF : 44 Pages View PDF
Philips Semiconductors
Universal Timeslot Interchange
Preliminary specification
SC2000
SR_11 is the MSB of this field.
Source Routing Memory MSB
Bit
0
1
2
3
4
5
6
7
Note:
Function
SR_8: Port Select 0
SR_9: Port Select 1
SR_10: Port Select 2
SR_11: Port Select 3
SR_12: Reserved
SR_13: Reserved
SR_14: Local Connect Enable
SR_15: Switch Output Enable
Bit 0 is the LSB of the High Byte
Data Register.
PEB Mode Source Data Stream
SR_11..SR_8 Source PEB Stream
0H
SERT Mux
1H
SERR
2H
R_SERT
3H
SERT
4H
Reserved
.
.
.
.
FH
Reserved
Local Connect Enable (SR_14): This bit
controls the internal connection time
slots on the local bus. When this bit is
cleared to 0 Local Connect is disabled.
When this bit is set to 1 Local Connect is
enabled and a time slot on the local SI
bus will be connected internally to a
time slot on the local SO bus.
When Local Connect is enabled the
Source Routing Memory Time slot
Select bits (SR_0 .. SR_6) select the
destination time slot on the local SO
bus. The contents of the Port Select
field (SR_8 .. SR_11) are ignored.
Switch Output Enable (SR_15): When
this bit is cleared to 0 the local SO bus
drivers are forced to the high impedance
state during the specified time slot pe-
riod. When this bit is set to 1 the local
SO bus drivers drive the bus during the
specified time slot period.
Destination Parallel Access Registers
(C0H .. DFH): If Parallel Access and
Switch Output are enabled, the device
CPU can write data to the expansion bus
via these SC2000 registers. The write
mapping is controlled by the Destina-
tion Routing Memory. The contents of
the selected Parallel Access Register will
replace the contents of the local SI bus
time slot that would otherwise have
been transferred to the expansion bus.
Destination Parallel Access Regs
IAR
C0H
C1H
C2H
.
.
DFH
Note:
SI Destination
Channel 0
Channel 1
Channel 2
.
.
Channel 31
IAR = Internal Address Register con-
tents. Channel N is equivalent to time
slot N on the local SI bus.
Source Parallel Access Registers
( E0H .. FFH): The Source Parallel
Access Registers are continually loaded
with the data being written to the corre-
sponding local SO bus time slot, irre-
spective of the status of the Parallel
Access Enable or Switch Output Enable
bits. If Local Connect is enabled this
data will originate from the local SI bus.
Source Parallel Access Regs
IAR
E0H
E1H
E2H
.
.
FFH
Note:
SO Destination
Channel 0
Channel 1
Channel 2
.
.
Channel 31
IAR = Internal Address Register con-
tents. Channel N is equivalent to time
slot N on the local SO bus.
2000 Sep 07
14
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