SC2000 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SC2000' PDF : 44 Pages View PDF
Philips Semiconductors
Universal Timeslot Interchange
Preliminary specification
SC2000
Table 4. Local Bus Interface Timing — SCbus Mode (4.096 Mbps)
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
t28
t29
t30
t31
t32
t33
t34
t35
Notes:
Parameter
Min
Typ
Max
Unit
SCLKx2* low time
61
ns
SCLKx2* high time
61
ns
SCLKx2* period
122
ns
SCLK low time
122
ns
SCLK high time
122
ns
SCLK period
244
ns
FSYNC* setup to SCLK ↑
0
ns
FSYNC* hold from SCLK↑
15
ns
SI_CLK ↓ delay from SCLK↑
40
ns
SI_CLK ↑delay from SCLK↓
40
ns
SO_CLK ↑delay from SCLK↑
40
ns
SO_CLK ↓delay from SCLK↑
40
ns
SI_FS, SI_MS ↓delay from SCLK↓
45
ns
SI_FS, SI_MS ↑delay from SCLK↓
45
ns
SO_FS, SO_MS↑delay from SCLK↑
45
ns
SO_FS, SO_MS↓ delay from SCLK↑
45
ns
SO float to valid delay from SCLK↑
40
ns
SO valid to valid delay from SCLK↑
40
ns
SO valid to float delay from SCLK↑
25
ns
SI setup to SCLK↑(50% sample position)
0
ns
SI hold from SCLK ↑ (50% sample position)
25
ns
SI setup to SCLK↓ (75% sample position)
0
ns
SI hold from SCLK ↓ (75% sample position)
25
ns
SD_[15:0] float to valid delay from SCLK↑
35
ns
SD_[15:0] valid to valid delay from SCLK↑
35
ns
SD_[15:0] valid to float delay from SCLK↑
25
ns
SD_[15:0] setup to SCLK↓(50% sample)
0
ns
SD_[15:0] hold from SCLK ↓ (50% sample)
25
ns
SD_[15:0] setup to SCLKx2*↑(75% sample) 0
ns
SD_[15:0] hold from SCLKx2* ↑(75% sample) 25
ns
TXD setup to SCLK↑ (registered MC)
0
ns
TXD hold from SCLK↑ (registered MC)
25
ns
MC delay from SCLK↑(registered MC)
85
ns
MC delay from TXD (passed through MC)
80
ns
RXD delay from MC
35
ns
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF load on all SCbus outputs.
2. MC timing measured with 200 pF, 470 Ω pullup (4.7 K Ω /10). Open collector low to high transitions include 61 ns delay from hi-Z to 2.4 V.
3. SI_CLK, SI_FS and SI_MS shown in ST-BUS framing format. When in PEB conventional framing format SI_CLK, SI_FS and SI_MS have
identical timing to SO_CLK, SO_FS and SO_MS.
4. SO shown configured as tri-state driver.
5. SO_MS, SI_MS are free-running multi-frame synchronization signals that occur once every 16 frames.
2000 Sep 07
21
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