SC2000 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SC2000' PDF : 44 Pages View PDF
Philips Semiconductors
Universal Timeslot Interchange
Preliminary specification
SC2000
Table 6.Local Bus Interface Timing — PEB Resource Module Without Switching
Symbol
t1a
t1b
t2a
t2b
t3a
t3b
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
Notes:
Parameter
Min
Typ
Max
Unit
CLKR, L_CLKT high time (1.544 Mbps)
323
ns
CLKR, L_CLKT high time (2.048 Mbps)
244
ns
CLKR, L_CLKT low time (1.544 Mbps)
323
ns
CLKR, L_CLKT low time (2.048 Mbps)
244
ns
CLKR, L_CLKT period (1.544 Mbps)
647
ns
CLKR, L_CLKT period (2.048 Mbps)
488
ns
SO_CLK ↑delay from CLKR ↑
35
ns
SO_CLK ↓delay from CLKR ↓
35
ns
SO_FS ↑delay from FSYNCR↑
35
ns
SO_FS ↓delay from FSYNCR↓
35
ns
SO_MS ↑delay from MSYNCR↑
35
ns
SO_MS ↓delay from MSYNCR↓
35
ns
SO delay from SERR
35
ns
SI_CLK ↑delay from L_CLKT ↑
35
ns
SI_CLK ↓delay from L_CLKT ↓
35
ns
L_FSYNCT setup to L_CLKT↓
5
ns
L_FSYNCT hold from L_CLKT↓
15
ns
SI_FS ↑delay from L_FSYNCT↑
35
ns
SI_FS ↓delay from L_FSYNCT↓
35
ns
SI_MS ↑delay from L_MSYNCT ↑
35
ns
SI_MS ↓delay from L_MSYNCT ↓
35
ns
L_SERT enable delay from L_CLKT ↑
70
ns
L_SERT delay from SI
60
ns
L_SERT disable delay from L_CLKT↑
70
ns
L_TSX* ↓ delay from L_CLKT↑
35
ns
L_TSX* ↑ delay from L_CLKT↑
70
ns
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions
include 43 ns delay from hi-Z to 2.4 V.
2. L_TSX* occurs on time slot boundaries.
2000 Sep 07
25
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