SC2000 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SC2000' PDF : 44 Pages View PDF
Philips Semiconductors
Universal Timeslot Interchange
Preliminary specification
SC2000
Table 9. Local Bus Interface Timing — PEB Network Module With Switching
Symbol
t1a
t1b
t2a
t2b
t3a
t3b
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
t18
t19
t20
t21
t22
t23
t24
t25
t26
t27
Notes:
Parameter
Min
Typ
Max
Unit
CLKR high time (1.544 Mbps)
323
ns
CLKR high time (2.048 Mbps)
244
ns
CLKR low time (1.544 Mbps)
323
ns
CLKR low time (2.048 Mbps)
244
ns
CLKR period (1.544 Mbps)
647
ns
CLKR period (2.048 Mbps)
488
ns
SO_CLK, SI_CLK↑ delay from CLKR ↑
35
ns
SO_CLK, SI_CLK↓ delay from CLKR ↓
35
ns
FSYNCR setup to CLKR ↓
5
ns
FSYNCR hold from CLKR ↓
15
ns
SO_FS, SI_FS↑ delay from FSYNCR ↑
35
ns
SO_FS, SI_FS↓ delay from FSYNCR ↓
35
ns
SO_MS ↑ delay from L_MSYNCT ↑
35
ns
SO_MS ↓ delay from L_MSYNCT ↓
35
ns
SI_MS ↑ delay from MSYNCR ↑
35
ns
SI_MS ↓ delay from MSYNCR ↓
35
ns
SO float to valid delay from CLKR ↑
40
ns
SO valid to valid delay from CLKR ↑
40
ns
SO valid to float delay from CLKR ↑
25
ns
SI setup to CLKR ↓
0
ns
SI hold from CLKR ↓
25
ns
SER enable delay from CLKR↑
70
ns
SER valid delay from CLKR ↑
70
ns
SER disable delay from CLKR↑
70
ns
SER setup to CLKR ↓
0
ns
SER hold from CLKR ↓
25
ns
TSX* ↓ delay from CLKR ↑
35
ns
TSX* ↑ delay from CLKR ↑
70
ns
TSX* setup to CLKR↓
0
ns
TSX* hold from CLKR ↓
25
ns
1. Timing measured with 100 pF load on all Local Bus outputs, 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions
include 43 ns delay from hi-Z to 2.4 V.
2. SER = L_SERT, SERR, R_SERT, SERT.
3. TSX* = L_TSX*, R_TSX*.
2000 Sep 07
31
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