SC2000 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SC2000' PDF : 44 Pages View PDF
Philips Semiconductors
Universal Timeslot Interchange
Preliminary specification
SC2000
Figure 15. PEB Network Slave
CLKT
t1
t2
t3
CLKR, L_CLKT
t4
t5
SYNC_IN
t7
t6
t9
t8
FSYNCT
FSYNCR, L_FSYNCT
t10
t11
MSYNCT
MSYNCR
t12 t14
t13 t15
L_MSYNCT
t16
t17
Table 15: PEB Network Slave
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
t14
t15
t16
t17
Note:
Parameter
Min
Typ
Max
Unit
CLKT period
488
ns
CLKT high time
244
ns
CLKT low time
244
ns
CLKR, L_CLKT ↑ delay from CLKT ↑
60
ns
CLKR, L_CLKT ↓ delay from CLKT ↓
25
ns
SYNC_IN low setup to CLKR ↓
0
ns
SYNC_IN low hold from CLKR ↓
20
ns
SYNC_IN high setup to CLKR ↓
0
ns
SYNC_IN high hold from CLKR ↓
20
ns
FSYNCR, L_FSYNCT ↑ delay from FSYNCT ↑
60
ns
FSYNCR, L_FSYNCT ↓ delay from FSYNCT ↓
25
ns
MSYNCR ↑ delay from MSYNCT ↑
60
ns
MSYNCR ↓delay from MSYNCT↓
25
ns
MSYNCR ↑ delay from CLKR ↑
70
ns
MSYNCR ↓ delay from CLKR ↑
35
ns
L_MSYNCT ↑ delay from MSYNCT ↑
60
ns
L_MSYNCT ↓ delay from MSYNCT ↓
25
ns
1. Timing measured with 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions include 43 ns delay from hi-Z to 2.4 V.
2000 Sep 07
39
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