SC2000 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SC2000' PDF : 44 Pages View PDF
Philips Semiconductors
Universal Timeslot Interchange
Figure 10. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider ≥4)
CLK_IN (Conventional)
t1
t2 t3
SYNC_IN (Conventional)
t4 t5
t6 t7
CLK_IN (ST-BUS)
SYNC_IN (ST-BUS)
SCLKX2*
SCLK
FSYNC*
t1
t2 t3
t8 t9
t10b
t11b
t10a
t11a
t12b
t13b
t12a
t13a
t14
t15
Table 10. CLK_IN, SYNC_IN — SCbus Mode (CLK_IN Divider ≥ 4)
Symbol
Parameter
Min
Typ
Max
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10a
t10b
t11a
t11b
t12a
t12b
t13a
t13b
t14
t15
Note:
CLK_IN period
122
CLK_IN high time
61
CLK_IN low time
61
SYNC_IN low setup to CLK_IN↓ (PEB conventional) 10
SYNC_IN low hold from CLK_IN↓ (PEB conventional) 10
SYNC_IN high setup to CLK_IN↓ (PEB conventional) 10
SYNC_IN high hold from CLK_IN↓ (PEB conventional) 10
SYNC_IN setup to CLK_IN↓ (ST-BUS)
10
SYNC_IN hold from CLK_IN ↓ (ST-BUS)
10
SCLKx2*↓ delay from CLK_IN ↑ (PEB conventional)
25
SCLKx2* ↓ delay from CLK_IN ↓ (ST-BUS)
25
SCLKx2*↑ delay from CLK_IN ↑ (PEB conventional)
25
SCLKx2* ↑ delay from CLK_IN ↓ (ST-BUS)
25
SCLK↑ delay from CLK_IN ↑ (PEB conventional)
25
SCLK↑ delay from CLK_IN ↓ (ST-BUS)
25
SCLK↓ delay from CLK_IN ↑ (PEB conventional)
25
SCLK↓ delay from CLK_IN ↓ (ST-BUS)
25
FSYNC*↓ delay from SCLKx2* ↑
30
FSYNC*↑ delay from SCLKx2* ↑
30
1. Timing measured with 200 pF load on all SCbus outputs.
Preliminary specification
SC2000
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
2000 Sep 07
32
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