SC2000 View Datasheet(PDF) - Philips Electronics
Part Name
Description
MFG CO.
'SC2000' PDF : 44 Pages View PDF
Philips Semiconductors
Universal Timeslot Interchange
Preliminary specification
SC2000
Table 14. CLK_IN, SYNC_IN — PEB Network Master Mode (CLK_IN Divider = 1)
Symbol
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10a
t10b
t11a
t11b
t12
t13
t14
t15
t16
t17
t18
t19
Note:
Parameter
Min
Typ
Max
Unit
CLK_IN period
488
ns
CLK_IN high time
244
ns
CLK_IN low time
244
ns
SYNC_IN low setup to CLK_IN↓ (PEB conventional)
10
ns
SYNC_IN low hold from CLK_IN↓ (PEB conventional)
10
ns
SYNC_IN high setup to CLK_IN ↓ (PEB conventional)
10
ns
SYNC_IN high hold from CLK_IN↓ (PEB conventional)
10
ns
SYNC_IN setup to CLK_IN↓ (ST-BUS)
10
ns
SYNC_IN hold from CLK_IN↓ (ST-BUS)
10
ns
CLKR, L_CLKT↑delay from CLK_IN↑(PEB conventional)
60
ns
CLKR, L_CLKT↑ delay from CLK_IN ↓(ST-BUS)
60
ns
CLKR, L_CLKT↓delay from CLK_IN↓(PEB conventional)
30
ns
CLKR, L_CLKT↓ delay from CLK_IN ↑(ST-BUS)
30
ns
FSYNCR, L_FSYNCT↑delay from CLKR ↑
70
ns
FSYNCR, L_FSYNCT↓delay from CLKR ↑
35
ns
MSYNCR ↑ delay from CLKR ↑
70
ns
MSYNCR ↓ delay from CLKR ↑
35
ns
L_MSYNCT ↑ delay from CLKR ↑
70
ns
L_MSYNCT ↓ delay from CLKR ↑
35
ns
L_MSYNCT ↑ delay from MSYNCT ↑
60
ns
L_MSYNCT↓ delay from MSYNCT ↓
25
ns
1. Timing measured with 200 pF 220/330 Ω termination on all PEB outputs. Open collector low to high transitions include 43 ns delay from hi-Z to 2.4 V.
2000 Sep 07
38
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