SC2446ITETRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC2446ITETRT' PDF : 38 Pages View PDF
SC2446
POWER MANAGEMENT
Application Information (Cont.)
The conduction losses are then
Pbc=IQ2,rms2 Rds(on).
where Rds(on) is the channel resistance of bottom MOSFET.
If the input voltage to output voltage ratio is high (e.g.
Vin=12V, Vo=1.5V), the duty ratio D will be small. Since the
bottom switch conducts with duty ratio (1-D), the
corresponding conduction losses can be quite high.
Due to non-overlapping conduction between the top and
the bottom MOSFET’s, the internal body diode or the
external Schottky diode across the drain and source
terminals always conducts prior to the turn on of the bottom
MOSFET. The bottom MOSFET switches on with only a diode
voltage between its drain and source terminals. The
switching loss
Pbs
=
1
2
(t
r
+ tf )(1+
δ
2
)Io
Vd
fs
is negligible due to near zero-voltage switching.
Integrated Power MOSFET Drivers
In SC2446 there are four internally integrated gate
drivers to drive all the MOSFETs in dual channels. With
the device bipolar process, emitter-follower based
Darlington bipolar transistors are used for the output
stage. The key advantage of the Darlington configuration
is that the total current gain is greatly improved which
leads to larger driving current Igs. This in turn will help
reduce the MOSFETs switching losses. In order to
estimate the losses associated with the gate driver, we
first measured the gate driver waveform (typical
waveforms of Vce and Igs) as shown in Figure12.
The gate losses are estimated as
Pbg
=
Rg
R gt
QgVcc fs.
The total bottom switch losses are then
Pb=Pbc+Pbs+Pbg.
Once the power losses Ploss for the top (Pt) and bottom (Pb)
MOSFET’s are known, thermal and package design at
component and system level should be done to verify that
the maximum die junction temperature (T , usually
j,max
125oC) is not exceeded under the worst-case condition.
The equivalent thermal impedance from junction to
ambient (θja) should satisfy
θ ja
≤
Tj,max − Ta,max
Ploss
.
θja depends on the die to substrate bonding, packaging
material, the thermal contact surface, thermal compound
property, the available effective heat sink area and the air
flow condition (free or forced convection). Actual temperature
measurement of the prototype should be carried out to
verify the thermal design.
Figure 12. Measured gate driver output waveforms
with 2.2Ω current limit resistor.
It is clear that the saturation voltage is not a constant. It
changes with the driving current in a nonlinear fashion.
A simple formula to calculate the losses with a reasonable
accuracy is not available. But, we use a curve fitting
technique to estimate the power losses in gate driver.
First, the saturation voltage vce(t) is approximated as
v ce (t)
=
−
Vcc 2
1 ( t )2
2 T1 .
Where, Vcc is the gate driver collector voltage, T1 is a time
constant related to the fall time of vce. For the example
in Fig. 12, Vcc=12V, T1=0.5Tf with Tf being measured as
~50 ns. With these parameters, the approximated vce(t) is
plotted as in Figure 13 a).
2004 Semtech Corp.
17
www.semtech.com
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