SC2446ITETRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC2446ITETRT' PDF : 38 Pages View PDF
SC2446
POWER MANAGEMENT
Application Information (Cont.)
In some initial prototypes, if the circuit noise makes the
control loop jittering, it is suggested to use a bigger C3
value than the calculated one here. Effectively, the
converter bandwidth is reduced in order to reject some
high frequency noises. In the final working circuit, the
loop transfer function should be measured using network
analyzer and compared with the design to ensure circuit
stability under different line and load conditions. The load
transient response behavior is further tested and
measured to meet the specification.
PC Board Layout Issues
Circuit board layout is very important for the proper
operation of high frequency switching power converters. A
power ground plane is required to reduce ground bounces.
The followings are suggested for proper layout.
4) Shorten the gate driver path. Integrity of the gate drive
(voltage level, leading and falling edges) is important for
circuit operation and efficiency. Short and wide gate drive
traces reduce trace inductances. Bond wire inductance
is about 2~3nH. If the length of the PCB trace from the
gate driver to the MOSFET gate is 1 inch, the trace
inductance will be about 25nH. If the gate drive current
is 2A with 10ns rise and falling times, the voltage drops
across the bond wire and the PCB trace will be 0.6V and
5V respectively. This may slow down the switching
transient of the MOSFET’s. These inductances may also
ring with the gate capacitance.
5) Put the decoupling capacitor for the gate drive power
supplies (BST and PVCC) close to the IC and power
ground.
Control Section
Power Stage
1) Separate the power ground from the signal ground. In
SC2446, the power ground PGND should be tied to the
source terminal of lower MOSFETs. The signal ground
AGND should be tied to the negative terminal of the
output capacitor.
2) Minimize the size of high pulse current loop. Keep the
top MOSFET, bottom MOSFET and the input capacitors
within a small area with short and wide traces. In addition
to the aluminum energy storage capacitors, add multi-
layer ceramic (MLC) capacitors from the input to the power
ground to improve high frequency bypass.
6) The frequency-setting resistor Rosc should be placed
close to Pin 3. Trace length from this resistor to the analog
ground should be minimized.
7) Solder the bias decoupling capacitor right across the
AVCC and analog ground AGND.
8) Place the Combi-sense components away from the
power circuit and close to the corresponding CS+ and CS-
pins. Use X7R type ceramic capacitor for the Combi-sense
capacitor because of their temperature stability.
9) Use an isolated local ground plane for the controller
and tie it to the negative side of output capacitor bank.
3) Reduce high frequency voltage ringing. Widen and
shorten the drain and source traces of the MOSFET’s to
reduce stray inductances. Add a small RC snubber if
necessary to reduce the high frequency ringing at the phase
node. Sometimes slowing down the gate drive signal also
helps in reducing the high frequency ringing at the phase
node.
2004 Semtech Corp.
25
www.semtech.com
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