SC401B
Applications Information (continued)
One-Shot Timer and Operating Frequency
The one-shot timer operates as shown in Figure 2. The FB
Comparator output goes high when VFB is less than the
internal 600mV reference. This feeds into the gate drive
and turns on the high-side MOSFET, and also starts the
one-shot timer. The one-shot timer uses an internal com-
parator and a capacitor. One comparator input is con-
nected to VOUT, the other input is connected to the
capacitor. When the on-time begins, the internal capaci-
tor charges from zero volts through a current which is
proportional to VIN. When the capacitor voltage reaches
VOUT, the on-time is completed and the high-side MOSFET
turns off.
FB
VREF
FB
Comparator
-
+
Gate
Drives VIN
DH
Q1
VLX L
VOUT
VIN
One-Shot
Timer
ESR
DL
Q2
COUT
+
RTON On-time = K x RTON x (VOUT/VIN)
VOUT
FB
Figure 2 — On-Time Generation
This method automatically produces an on-time that is
proportional to VOUT and inversely proportional to VIN.
Under steady-state conditions, the switching frequency
can be determined from the on-time by the following
equation.
fSW
VOUT
TON u VIN
The SC401B uses an external resistor to set the on-time
which indirectly sets the frequency. The on-time can be
programmed to provide an operating frequency up to
1MHz using a resistor between the TON pin and ground.
The resistor value is selected by the following equation.
RTON
k
25pF u fSW
The constant, k, equals 1 when VDD is greater than 3.6V. If
VDD is less than 3.6V and VIN is greater than (VDD -1.75) x 10,
k is shown by the following equation.
k VDD 1.75u10
VIN
The maximum RTON value allowed is shown by the follow-
ing equation.
RTON _ MAX
VIN _ MIN
15PA
VOUT Voltage Selection
The switcher output voltage is regulated by comparing
VOUT as seen through a resistor divider at the FB pin to the
internal 600mV reference voltage, see Figure 3.
VOUT
To FB pin
R1
R2
Figure 3 — Output Voltage Selection
Note that this control method regulates the valley of the
output ripple voltage, not the DC value. The DC output
voltage VOUT is offset by the output ripple according to the
following equation.
VOUT
0.6
u
¨¨©§1
R1
R2
¸¸¹·
¨§
©
VRIPPLE
2
¸·
¹
When a large capacitor is placed in parallel with R1 (CTOP)
VOUT is shown by the following equation.
VOUT
0.6
u
¨¨©§1
R1
R2
¸¸¹·
¨§
©
VRIPPLE
2
¸·
¹
u
1 (R1ZCTOP )2
1
¨¨©§
R2
R2
u
R1
R1
ZCTOP
¸¸¹·2
Enable and Power Save Inputs
The EN/PSV input is used to enable or disable the switch-
ing regulator. When EN/PSV is low (grounded), the switch-
ing regulator is off and in its lowest power state. When off,
the output of the switching regulator soft-discharges the
output into a 15Ω internal resistor via the VOUT pin. When
EN/PSV is allowed to float, the pin voltage will float to 33%
of the voltage at VDD. The switching regulator turns on
with power save disabled and all switching is in forced
continuous mode.
When EN/PSV is high (above 44% of the voltage at VDD),
the switching regulator turns on with power save enabled.
17