SC403MLTRT View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC403MLTRT' PDF : 32 Pages View PDF
SC403
Applications Information (continued)
PCB Layout Guidelines
The optimum layout for the SC403 is shown in Figure 15.
This layout shows an integrated FET buck regulator with a
maximum current of 6A. The total PCB area is approxi-
mately 20 x 25 mm.
Critical Layout Guidelines
The following critical layout guidelines must be followed
to ensure proper performance of the device.
• IC decoupling capacitors
• PGND plane
• AGND island
• FB, VOUT, and other analog control signals
• BST, ILIM, and LX
• CIN and COUT placement and current loops
IC Decoupling Capacitors
• A 0.1 μF capacitor must be located as close as
possible to the IC and directly connected to pins
3 (VDD) and 4 (AGND).
• All other decoupling capacitors must be located
as close as possible to the IC.
PGND Plane
• PGND requires its own copper plane with no
other signal traces routed on it.
• Copper planes, multiple vias and wide traces are
needed to connect PGND to input capacitors,
output capacitors, and the PGND pins on the
device.
• The PGND copper area between the input
capacitors, output capacitors, and PGND pins
must be as tight and compact as possible to
reduce the area of the PCB that is exposed to
noise due to current flow on this node.
• Connect PGND to AGND with a short trace or
0Ω resistor. This connection should be as close
to the device as possible.
V5V Decoupling Capacitor
AGND plane on
inner layer
RGND — AGND connects to
PGND close to the IC
RLDO2 RLDO1
RILIM
RGND
All components
shown Top Side
RFB1
CFF
CLDO
RFB2
PGND on
Top Layer
CIN
COUT
VOUT Plane
on Top layer
L
PGND
Pin 1 marking
IC with vias for
LX, AGND, VIN
VIN plane on inner
or bottom layer
PGND on inner
or bottom layer
LX plane on inner
or bottom layer
Figure 15 — PCB Layout
28
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