SC417/SC427
Applications Information (continued)
inductor. If the load di/dt is not much faster than the -di/
dt in the inductor, then the inductor current will tend to
track the falling load current. This will reduce the excess
inductive energy that must be absorbed by the output
capacitor, therefore a smaller capacitance can be used.
The following can be used to calculate the needed capaci-
tance for a given dILOAD/dt:
Peak inductor current is shown by the next equation.
ILPK = IMAX + 1/2 x IRIPPLEMAX
ILPK = 10 + 1/2 x 4.4 = 12.2A
Rate of change of Load Current dlLOAD
dt
IMAX = maximum load release = 10A
COUT
Lu ILPK IMAX u dt
ILPK u
VOUT dlLOAD
2 VPK VOUT
Example
Load dlLOAD
dt
2.5A
Ps
This would cause the output current to move from 10A to
zero in 4μs as shown by the following equation.
COUT
0.88PHu 12.2 10 u1Ps
12.2 u
1.05 2.5
21.15 1.05
Stability Considerations
Unstable operation is possible with adaptive on-time con-
trollers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
250ns minimum off-time has expired. In extreme cases
the noise can cause three or more successive on-times.
Double-pulsing will result in higher ripple voltage at the
output, but in most applications it will not affect opera-
tion. This form of instability can usually be avoided by
providing the FB pin with a smooth, clean ripple signal
that is at least 10mVp-p, which may dictate the need to
increase the ESR of the output capacitors. It is also impera-
tive to provide a proper PCB layout as discussed in the
Layout Guidelines section.
Another way to eliminate doubling-pulsing is to add a
small (~ 10pF) capacitor across the upper feedback resis-
tor, as shown in Figure 13. This capacitor should be left
unpopulated until it can be confirmed that double-pulsing
exists. Adding the C capacitor will couple more ripple
TOP
into FB to help eliminate the problem. An optional con-
nection on the PCB should be available for this capacitor.
CTOP
VOUT
R1
To FB pin
R2
C = 379 μF
OUT
Note that C is much smaller in this example, 379μF
OUT
compared to 595μF based on a worst-case load release. To
meet the two design criteria of minimum 379μF and
maximum 9mΩ ESR, select two capacitors rated at 220μF
and 15mΩ ESR.
It is recommended that an additional small capacitor be
placed in parallel with COUT in order to filter high frequency
switching noise.
Figure 13 — Capacitor Coupling to FB Pin
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking sta-
bility is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
22