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SC417EVB View Datasheet(PDF) - Semtech Corporation

Part Name
Description
MFG CO.
'SC417EVB' PDF : 29 Pages View PDF
SC417/SC427
Applications Information (continued)
PCB Layout Guidelines
The optimum layout for the SC417/SC427 is shown in
Figure 15. The layout highlights the device as a space
saving and high performance solution. This layout shows
an integrated FET buck regulator with a maximum current
of 10A. The total PCB area is approximately 20 x 25 mm.
This figure shows the total area and optimum layout for
the device. If optimum layout is not possible due to PCB
limitations, the following generic guidelines should be
followed.
AGND should connect to PGND (power ground) using an
external zero ohm resistor or using a short PCB trace.
Connect AGND to PGND only at one place, as near to the
AGND and PGND pins as is practical.
Power ground (PGND) should be a separate plane which is
not used for routing analog traces.
All PGND connections should connect directly to the
PGND plane. Indirect connections between AGND and
GND which will create ground loops should be avoided.
Generic Layout Guidelines
One or more ground planes are recommended to mini-
mize the effect of switching noise, resistive losses, and to
maximize heat removal. The analog ground reference
AGND should connect directly to the AGND pad and pins.
An AGND plane or island should be used near the device.
All components that are referenced to AGND should
connect directly to this plane and mounted on the IC side
of the PCB.
The V5V input provides power to the internal analog cir-
cuits and the upper and lower gate drivers. The V5V supply
decoupling capacitors should be tied between V5V and
PGND with short traces.
The switcher power section should be connected directly
to the PGND plane(s) using multiple vias as required for
AGND plane on
inner layer
All components
shown Top Side
PGND
RGND — AGND connects to
PGND close to SC417/SC427
RLDO2 RLDO1
CLDO
RFB1
CFF
RFB2
CIN
RILIM
Pin 1 marking
SC417/SC427
with vias for LX,
AGND, VIN
VIN plane on inner
or bottom layer
VOUT Plane
on Top layer
PGND on
Top layer
COUT
L
Figure 15 — PCB Layout
PGND on inner
or bottom layer
LX plane on inner
or bottom layer
25
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