SC453
POWER MANAGEMENT
Applications Information (Cont.)
Step 4: BOOTV Design
The boot-up voltage for VCORE is set at 1.2V. For the SC453
typical application circuit, R3, R4, and R5 form a voltage
divider off V and are used to set the boot voltage. For
REF
simplicity, we define RBOOT : = R3 + R4.
⎛⎜ R14⋅RHYS ⎞
⎜ R14 − RHYS ⎟
v := ⎜
⎟
⎜0 ⎟
⎜⎝ 0 ⎟⎠
VBOOT := 1.2V
O.
1
RHYS := 1
1
+
R25 RBOOT + R5
P.
VBOOT⋅R5
RBOOT := VREF − VBOOT
Step 5: Sleep Voltage Design
The sleep voltage is set at 0.750V nominally using the R3
- R4 - R5 divider.
( ) soln := lsolve Mx, v
⎛
⎜
5.011
×
4
10
⎞
soln
=
⎜
⎜ 3.007
×
4
10
⎟
⎟
Ω
⎜
⎝ 3.341
×
4
10
⎟
⎠
R3 := (1 0 0 )⋅soln
R4 := (0 1 0 )⋅soln
R5 := (0 0 1 )⋅soln
R3
=
5.011
×
4
10
Ω
R4
=
3.007
×
4
10
Ω
R5
=
3.341
×
4
10
Ω
From the standard 1% resistor value table, we choose
the following values according to the calculation results:
Q.
VSLP := 0.750 V
(R4 + R5)
R3 := VSLP⋅ VREF − VSLP
R3, R4 and R5 are calculated using a matrix to solve the
simultaneous equations. R14 is set at 1MΩ as a place-
holder:
R14 := 1000 KΩ
R5 = 33.2KΩ.
R4 = 30.1KΩ
R3 = 49.9KΩ
Step 6: Current Limit Calculation
Setting the threshold for current limit is a relatively
straightforward process. To do this we must calculate the
peak current based on the maximum DC value plus the
worst-case ripple current. The following calculations apply
for a single phase. Worst-case ripple occurs at the high-
est input voltage. Since ripple is also inversely proportion-
al to inductance, it is recommended that the minimum
inductance value be used based on the manufacturer’s
specified tolerance:
⎛1
⎜
⎜
Mx
:=
⎜
⎜
1
⎜
⎜1
⎝
1
1
−1
VSLP⋅ VREF − VSLP
1
⎞
VBOOT
⎟
−
VREF − VBOOT
⎟
⎟
−1 ⎟
VSLP⋅
VREF
−
VSLP
⎟
⎠
LLOW := L1⋅(1 − 20%)
LLOW
=
4.8
×
−
10
7
H
R.
( ) VINMAX − VMAX_NL ⋅dMIN
IRIPPLE_MAX :=
LLOW⋅FS
IRIPPLE_MAX = 6.777 A
© 2006 Semtech Corp.
18
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