SC461 View Datasheet(PDF) - Semtech Corporation
Part Name
Description
MFG CO.
'SC461' PDF : 31 Pages View PDF
SC461
Applications Information (continued)
Another way to eliminate doubling-pulsing is to add a
small capacitor across the upper feedback resistor, as
shown in Figure 16. This capacitor should be left unpopu-
lated unless it can be confirmed that double-pulsing
exists. Adding the CTOP capacitor will couple more ripple
into FB to help eliminate the problem. An optional con-
nection on the PCB should be available for this capacitor.
charging during the switching cycle. For most applica-
tions the minimum ESR ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching fre-
quency. The formula for minimum ESR is shown by the
following equation.
CTOP
ESRMIN
3
2 u S u COUT u fsw
VOUT
R1
To FB pin
R2
Figure 16 — Capacitor Coupling to FB Pin
NOTE: The CTOP capacitor can moderately affect the DC output volt-
age, refer to the section on VOUT voltage selection.
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking sta-
bility is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
One simple way to solve this problem is to add trace resis-
tance in the high current output path. A side effect of
adding trace resistance is decreased load regulation.
ESR Requirements
A minimum ESR is required for two reasons. One reason is
to generate enough output ripple voltage to provide
10mVp-p at the FB pin (after the resistor divider) to avoid
double-pulsing.
The second reason is to prevent instability due to insuffi-
cient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and dis-
Using Ceramic Output Capacitors
When using high ESR value capacitors, the feedback
voltage ripple lags the phase node voltage by 90 degrees
and the converter is easily stabilized. When using ceramic
output capacitors, the ESR value is normally too small to
meet the above ESR criteria. As a result, the feedback
voltage ripple is 180 degrees from the phase node leading
to unstable operation. In this application it is necessary to
add a small virtual ESR network that is composed of two
capacitors and one resistor, as shown by RL, CL, and CC in
Figure 17.
L
DCR
RL VL CL
CC
+- D x VIN
FB
pin
R1
COUT
R2
Figure 17 — Virtual ESR Ramp Circuit
The ripple voltage at FB is a superposition of two voltage
sources: the voltage across CL and the output ripple
voltage. They are defined in the following equations.
9F/
,/ u'&5 V u/ '&5
6 u 5/&/
'9287
' ,/
& u I6:
Figure 18 shows the equivalent circuit for calculating the
magnitude of the ripple contribution at the FB pin due to CL.
24
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